2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) Siemens AG, 2013
5 * Copyright (c) Valentine Sinitsyn, 2014
8 * Jan Kiszka <jan.kiszka@siemens.com>
9 * Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
11 * This work is licensed under the terms of the GNU GPL, version 2. See
12 * the COPYING file in the top-level directory.
15 #ifndef _JAILHOUSE_ASM_CELL_H
16 #define _JAILHOUSE_ASM_CELL_H
18 #include <jailhouse/paging.h>
20 #include <jailhouse/cell-config.h>
24 /** x86-specific cell states. */
26 /** Buffer for the EPT/NPT root-level page table. */
27 u8 __attribute__((aligned(PAGE_SIZE))) root_table_page[PAGE_SIZE];
31 /** PIO access bitmap. */
33 /** Paging structures used for cell CPUs. */
34 struct paging_structures ept_structs;
35 } vmx; /**< Intel VMX-specific fields. */
37 /** I/O Permissions Map. */
39 /** Paging structures used for cell CPUs. */
40 struct paging_structures npt_structs;
41 } svm; /**< AMD SVM-specific fields. */
46 /** Paging structures used for DMA requests. */
47 struct paging_structures pg_structs;
48 /** True if interrupt remapping support is emulated for this
51 } vtd; /**< Intel VT-d specific fields. */
53 /** Paging structures used for DMA requests. */
54 struct paging_structures pg_structs;
55 } amd_iommu; /**< AMD IOMMU specific fields. */
58 /** Shadow value of PCI config space address port register. */
59 u32 pci_addr_port_val;
61 /** List of IOAPICs assigned to this cell. */
62 struct cell_ioapic *ioapics;
63 /** Number of assigned IOAPICs. */
64 unsigned int num_ioapics;
66 /** Class Of Service for cache allocation (Intel only). */
68 /** Allocated L3 cache region (Intel only). */
72 #endif /* !_JAILHOUSE_ASM_CELL_H */