arm: tegra12: dfll clock rate variable update

arm: tegra12: dfll clock rate variable update

Update c->rate with the requested rate.
Rate returned by tegra_cl_dvfs_request_get rounded to DFLL granularity.
This commit ensures correct clock  settings when switching back and
forth to a clock source with different granularity.

Bug 200039843

Change-Id: If58a9426e01ac79dd3b11053da56d075e834a710
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/504604
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>