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(parent: 2aa8aa6) | patch
arm64: enable EL0 access to performance monitors
authorBo Yan <byan@nvidia.com>
Tue, 5 Aug 2014 00:07:53 +0000 (17:07 -0700)
committerIshan Mittal <imittal@nvidia.com>
Mon, 14 Mar 2016 10:20:23 +0000 (15:50 +0530)
commitde18c2fd0d9e6bf0eb93c833b6c4197a9eaaf4cf
tree400c072b0d4378261a98ed3dfe3605e89a8c21aatree | snapshot
parent2aa8aa6fd4643be042ffa57c236071a931eaef43commit | diff
arm64: enable EL0 access to performance monitors

If PERF_EVENT is enabled, the user space access to PMU registers
is disabled in reset function. Enable it so user space apps can
still access performance monitors.

Change-Id: Id63ff82145cd1d7e97b171672a823bce367587ef
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/451176
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
arch/arm64/kernel/perf_event.c diff | blob | history