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tegra: powergate: cleanup clock and reset handling
authorPeter De Schrijver <pdeschrijver@nvidia.com>
Fri, 16 Sep 2016 10:56:31 +0000 (13:56 +0300)
committermobile promotions <svcmobile_promotions@nvidia.com>
Tue, 20 Sep 2016 09:59:09 +0000 (02:59 -0700)
commitbb10919f7e9472ba025c10351bf2a412e7005419
tree330b5bb24467daadea0febb13963218c0f8a7956tree | snapshot
parentdd2b7b8cdcb284bd1c80444ce4216a30697795fecommit | diff
tegra: powergate: cleanup clock and reset handling

Stop looking for clocks when we hit an error or NULL clock pointer.
Resets now use the tegra_rst_assertv/tegra_rst_deassertv so no loop is
necessary.

Change-Id: I18dc6e310ff22522dc765d47394e2de4b1b8a894
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1221928
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
drivers/platform/tegra/powergate/powergate.c diff | blob | history