mmc: tegra: Reset sdhci controller.

mmc: tegra: Reset sdhci controller.

-Assert and Deassert sdhci controller to clear all previous status.
-SDMMC_SPARE0[7:6] should not be touched by SW.
-Disabling these bits will lead to undefined behavior of SDMMC and
may see data CRC issues or hang issues.
-Kernel SW is not clearing SDMMC_SPARE0[7:6], but while reading the
register in probe the value is not set to reset value.

Bug 200093682

Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/728781
(cherry picked from commit 83b23127cf3a97daee53a730158b384f2a4e29ee)
Change-Id: I1f17aa1f469f7d166165e394ac570a4d54a20883
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/740030
Reviewed-by: Automatic_Commit_Validation_User