From 8476a24ca26ba0bf99d2dcc512260c2d0a8c765f Mon Sep 17 00:00:00 2001
From: Martin Jerabek <jerabma7@fel.cvut.cz>
Date: Fri, 13 May 2016 01:54:09 +0200
Subject: [PATCH] can_crossbar: fixes (but still not working)

---
 system/ip/can_crossbar_1.0/component.xml      | 10 ++--
 .../hdl/can_crossbar_v1_0_S00_AXI.v           | 48 +++++++++----------
 2 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/system/ip/can_crossbar_1.0/component.xml b/system/ip/can_crossbar_1.0/component.xml
index 94e1522..95b512e 100644
--- a/system/ip/can_crossbar_1.0/component.xml
+++ b/system/ip/can_crossbar_1.0/component.xml
@@ -266,7 +266,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>73ee1312</spirit:value>
+            <spirit:value>f744e7b0</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -282,7 +282,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>73ee1312</spirit:value>
+            <spirit:value>f744e7b0</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1026,8 +1026,8 @@
         <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
       </xilinx:taxonomies>
       <xilinx:displayName>can_crossbar_v1.0</xilinx:displayName>
-      <xilinx:coreRevision>3</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2016-05-12T00:55:21Z</xilinx:coreCreationDateTime>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2016-05-12T18:37:17Z</xilinx:coreCreationDateTime>
       <xilinx:tags>
         <xilinx:tag xilinx:name="user.org:user:can_crossbar:1.0_ARCHIVE_LOCATION">/home/martin/projects/cvut/bakalarka/canbench-sw/system/ip/can_crossbar_1.0</xilinx:tag>
       </xilinx:tags>
@@ -1036,7 +1036,7 @@
       <xilinx:xilinxVersion>2016.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="d9a0b4b8"/>
       <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="493665f4"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="37646b60"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c3c99675"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="94557fa6"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="4429bb0c"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="7691242a"/>
diff --git a/system/ip/can_crossbar_1.0/hdl/can_crossbar_v1_0_S00_AXI.v b/system/ip/can_crossbar_1.0/hdl/can_crossbar_v1_0_S00_AXI.v
index 6e04630..9a384bc 100644
--- a/system/ip/can_crossbar_1.0/hdl/can_crossbar_v1_0_S00_AXI.v
+++ b/system/ip/can_crossbar_1.0/hdl/can_crossbar_v1_0_S00_AXI.v
@@ -54,23 +54,23 @@ assign ifc_rx[3] = line_rx[ifc4_line];
 
 assign line_rx[0] = ~can_en[0] ? 1'b1 :
                    (can1_line == 0 ? can_rx[0] : 1'b1)
-                 & (can1_line == 1 ? can_rx[1] : 1'b1)
-                 & (can1_line == 2 ? can_rx[2] : 1'b1)
-                 & (can1_line == 3 ? can_rx[3] : 1'b1);
+                 & (can2_line == 0 ? can_rx[1] : 1'b1)
+                 & (can3_line == 0 ? can_rx[2] : 1'b1)
+                 & (can4_line == 0 ? can_rx[3] : 1'b1);
 assign line_rx[1] = ~can_en[1] ? 1'b1 :
-                   (can2_line == 0 ? can_rx[0] : 1'b1)
+                   (can1_line == 1 ? can_rx[0] : 1'b1)
                  & (can2_line == 1 ? can_rx[1] : 1'b1)
-                 & (can2_line == 2 ? can_rx[2] : 1'b1)
-                 & (can2_line == 3 ? can_rx[3] : 1'b1);
+                 & (can3_line == 1 ? can_rx[2] : 1'b1)
+                 & (can4_line == 1 ? can_rx[3] : 1'b1);
 assign line_rx[2] = ~can_en[2] ? 1'b1 :
-                   (can3_line == 0 ? can_rx[0] : 1'b1)
-                 & (can3_line == 1 ? can_rx[1] : 1'b1)
+                   (can1_line == 2 ? can_rx[0] : 1'b1)
+                 & (can2_line == 2 ? can_rx[1] : 1'b1)
                  & (can3_line == 2 ? can_rx[2] : 1'b1)
-                 & (can3_line == 3 ? can_rx[3] : 1'b1);
+                 & (can4_line == 2 ? can_rx[3] : 1'b1);
 assign line_rx[3] = ~can_en[3] ? 1'b1 :
-                   (can4_line == 0 ? can_rx[0] : 1'b1)
-                 & (can4_line == 1 ? can_rx[1] : 1'b1)
-                 & (can4_line == 2 ? can_rx[2] : 1'b1)
+                   (can1_line == 3 ? can_rx[0] : 1'b1)
+                 & (can2_line == 3 ? can_rx[1] : 1'b1)
+                 & (can3_line == 3 ? can_rx[2] : 1'b1)
                  & (can4_line == 3 ? can_rx[3] : 1'b1);
 
 /*
@@ -101,20 +101,20 @@ assign can_tx[2] = can_en[2] ? line_tx[can3_line] : 1'b1;
 assign can_tx[3] = can_en[3] ? line_tx[can4_line] : 1'b1;
 
 assign line_tx[0] = (ifc1_line == 0 ? ifc_tx[0] : 1'b1)
-                  & (ifc1_line == 1 ? ifc_tx[1] : 1'b1)
-                  & (ifc1_line == 2 ? ifc_tx[2] : 1'b1)
-                  & (ifc1_line == 3 ? ifc_tx[3] : 1'b1);
-assign line_tx[1] = (ifc2_line == 0 ? ifc_tx[0] : 1'b1)
+                  & (ifc2_line == 0 ? ifc_tx[1] : 1'b1)
+                  & (ifc3_line == 0 ? ifc_tx[2] : 1'b1)
+                  & (ifc4_line == 0 ? ifc_tx[3] : 1'b1);
+assign line_tx[1] = (ifc1_line == 1 ? ifc_tx[0] : 1'b1)
                   & (ifc2_line == 1 ? ifc_tx[1] : 1'b1)
-                  & (ifc2_line == 2 ? ifc_tx[2] : 1'b1)
-                  & (ifc2_line == 3 ? ifc_tx[3] : 1'b1);
-assign line_tx[2] = (ifc3_line == 0 ? ifc_tx[0] : 1'b1)
-                  & (ifc3_line == 1 ? ifc_tx[1] : 1'b1)
+                  & (ifc3_line == 1 ? ifc_tx[2] : 1'b1)
+                  & (ifc4_line == 1 ? ifc_tx[3] : 1'b1);
+assign line_tx[2] = (ifc1_line == 2 ? ifc_tx[0] : 1'b1)
+                  & (ifc2_line == 2 ? ifc_tx[1] : 1'b1)
                   & (ifc3_line == 2 ? ifc_tx[2] : 1'b1)
-                  & (ifc3_line == 3 ? ifc_tx[3] : 1'b1);
-assign line_tx[3] = (ifc4_line == 0 ? ifc_tx[0] : 1'b1)
-                  & (ifc4_line == 1 ? ifc_tx[1] : 1'b1)
-                  & (ifc4_line == 2 ? ifc_tx[2] : 1'b1)
+                  & (ifc4_line == 2 ? ifc_tx[3] : 1'b1);
+assign line_tx[3] = (ifc1_line == 3 ? ifc_tx[0] : 1'b1)
+                  & (ifc2_line == 3 ? ifc_tx[1] : 1'b1)
+                  & (ifc3_line == 3 ? ifc_tx[2] : 1'b1)
                   & (ifc4_line == 3 ? ifc_tx[3] : 1'b1);
 
 endmodule
-- 
2.39.2