From: Michal Sojka Date: Thu, 5 Sep 2019 08:56:36 +0000 (+0200) Subject: Replace dcsimpledrv_to_pmod12_pins with direct connection to PMOD pins X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/zynq/canbench-sw.git/commitdiff_plain/refs/heads/microzed_apo_psr Replace dcsimpledrv_to_pmod12_pins with direct connection to PMOD pins This change allows us to get rid of the following synthesis error (tested in Vivado 2017.3 and 2019.1): [Designutils 20-1595] In entity top_dcsimpledrv_to_pmod12_pins_0_0, connectivity of net PWM1_A cannot be represented in VHDL. VHDL lacks syntax to connect the following inout terminals to a differently-named net: inout FPGA_IO_C[39] Resolution: Check whether terminals really need inout direction and substitute input or output as needed. It may also be possible to rename the net to match the terminal. --- diff --git a/system/src/constrs/microzed_apo-rev1.xdc b/system/src/constrs/microzed_apo-rev1.xdc index bd1e248..c548cc0 100644 --- a/system/src/constrs/microzed_apo-rev1.xdc +++ b/system/src/constrs/microzed_apo-rev1.xdc @@ -61,47 +61,52 @@ set_property PACKAGE_PIN R19 [get_ports {SPEAKER}]; # JX1_SE_0 (34) set_property DIRECTION OUT [get_ports [list {SPEAKER}]]; # ------------------------------------------------------------------------------ -# FPGA IO connector and PMOD1 and 2 -# ------------------------------------------------------------------------------ - -set_property PACKAGE_PIN N18 [get_ports {FPGA_IO_A[1]}]; # JX1_LVDS_12_P (34) -set_property PACKAGE_PIN P19 [get_ports {FPGA_IO_A[2]}]; # JX1_LVDS_12_N (34) -set_property PACKAGE_PIN T11 [get_ports {FPGA_IO_A[3]}]; # JX1_LVDS_0_P (34) -set_property PACKAGE_PIN T10 [get_ports {FPGA_IO_A[4]}]; # JX1_LVDS_0_N (34) -set_property PACKAGE_PIN U13 [get_ports {FPGA_IO_A[5]}]; # JX1_LVDS_2_P (34) -set_property PACKAGE_PIN V13 [get_ports {FPGA_IO_A[6]}]; # JX1_LVDS_2_N (34) -set_property PACKAGE_PIN T14 [get_ports {FPGA_IO_A[7]}]; # JX1_LVDS_4_P (34) -set_property PACKAGE_PIN T15 [get_ports {FPGA_IO_A[8]}]; # JX1_LVDS_4_N (34) -set_property PACKAGE_PIN Y16 [get_ports {FPGA_IO_A[9]}]; # JX1_LVDS_6_P (34) -set_property PACKAGE_PIN Y17 [get_ports {FPGA_IO_A[10]}]; # JX1_LVDS_6_N (34) - -set_property PACKAGE_PIN T16 [get_ports {FPGA_IO_B[13]}]; # JX1_LVDS_8_P (34) -set_property PACKAGE_PIN U17 [get_ports {FPGA_IO_B[14]}]; # JX1_LVDS_8_N (34) -set_property PACKAGE_PIN U14 [get_ports {FPGA_IO_B[15]}]; # JX1_LVDS_10_P (34) -set_property PACKAGE_PIN U15 [get_ports {FPGA_IO_B[16]}]; # JX1_LVDS_10_N (34) -set_property PACKAGE_PIN T20 [get_ports {FPGA_IO_B[17]}]; # JX1_LVDS_14_P (34) -set_property PACKAGE_PIN U20 [get_ports {FPGA_IO_B[18]}]; # JX1_LVDS_14_N (34) -set_property PACKAGE_PIN Y18 [get_ports {FPGA_IO_B[19]}]; # JX1_LVDS_16_P (34) -set_property PACKAGE_PIN Y19 [get_ports {FPGA_IO_B[20]}]; # JX1_LVDS_16_N (34) -set_property PACKAGE_PIN R16 [get_ports {FPGA_IO_B[21]}]; # JX1_LVDS_18_P (34) -set_property PACKAGE_PIN R17 [get_ports {FPGA_IO_B[22]}]; # JX1_LVDS_18_N (34) -set_property PACKAGE_PIN V17 [get_ports {FPGA_IO_B[23]}]; # PMOD1[6] JX1_LVDS_20_P (34) -set_property PACKAGE_PIN V18 [get_ports {FPGA_IO_B[24]}]; # PMOD1[7] JX1_LVDS_20_N (34) -set_property PACKAGE_PIN N17 [get_ports {FPGA_IO_B[25]}]; # PMOD1[4] JX1_LVDS_22_P (34) -set_property PACKAGE_PIN P18 [get_ports {FPGA_IO_B[26]}]; # PMOD1[5] JX1_LVDS_22_N (34) -set_property PACKAGE_PIN P15 [get_ports {FPGA_IO_B[27]}]; # PMOD2[2] JX1_LVDS_23_P (34) -set_property PACKAGE_PIN P16 [get_ports {FPGA_IO_B[28]}]; # PMOD2[3] JX1_LVDS_23_N (34) - -set_property PACKAGE_PIN W18 [get_ports {FPGA_IO_C[31]}]; # PMOD2[0] JX1_LVDS_21_P (34) -set_property PACKAGE_PIN W19 [get_ports {FPGA_IO_C[32]}]; # PMOD2[1] JX1_LVDS_21_N (34) -set_property PACKAGE_PIN T17 [get_ports {FPGA_IO_C[33]}]; # PMOD2[4] JX1_LVDS_19_P (34) -set_property PACKAGE_PIN R18 [get_ports {FPGA_IO_C[34]}]; # PMOD2[5] JX1_LVDS_19_N (34) -set_property PACKAGE_PIN V16 [get_ports {FPGA_IO_C[35]}]; # PMOD2[6] JX1_LVDS_17_P (34) -set_property PACKAGE_PIN W16 [get_ports {FPGA_IO_C[36]}]; # PMOD2[7] JX1_LVDS_17_N (34) -set_property PACKAGE_PIN V20 [get_ports {FPGA_IO_C[37]}]; # PMOD1[2] JX1_LVDS_15_P (34) -set_property PACKAGE_PIN W20 [get_ports {FPGA_IO_C[38]}]; # PMOD1[3] JX1_LVDS_15_N (34) -set_property PACKAGE_PIN N20 [get_ports {FPGA_IO_C[39]}]; # PMOD1[0] JX1_LVDS_13_P (34) -set_property PACKAGE_PIN P20 [get_ports {FPGA_IO_C[40]}]; # PMOD1[1] JX1_LVDS_13_N (34) +# FPGA IO connector +# ------------------------------------------------------------------------------ + +# ------------------------------------------------------------------------------ +# PMOD1 and 2 +# ------------------------------------------------------------------------------ + + +# set_property PACKAGE_PIN N18 [get_ports {FPGA_IO_A[1]}]; # JX1_LVDS_12_P (34) +# set_property PACKAGE_PIN P19 [get_ports {FPGA_IO_A[2]}]; # JX1_LVDS_12_N (34) +# set_property PACKAGE_PIN T11 [get_ports {FPGA_IO_A[3]}]; # JX1_LVDS_0_P (34) +# set_property PACKAGE_PIN T10 [get_ports {FPGA_IO_A[4]}]; # JX1_LVDS_0_N (34) +# set_property PACKAGE_PIN U13 [get_ports {FPGA_IO_A[5]}]; # JX1_LVDS_2_P (34) +# set_property PACKAGE_PIN V13 [get_ports {FPGA_IO_A[6]}]; # JX1_LVDS_2_N (34) +# set_property PACKAGE_PIN T14 [get_ports {FPGA_IO_A[7]}]; # JX1_LVDS_4_P (34) +# set_property PACKAGE_PIN T15 [get_ports {FPGA_IO_A[8]}]; # JX1_LVDS_4_N (34) +# set_property PACKAGE_PIN Y16 [get_ports {FPGA_IO_A[9]}]; # JX1_LVDS_6_P (34) +# set_property PACKAGE_PIN Y17 [get_ports {FPGA_IO_A[10]}]; # JX1_LVDS_6_N (34) + +# set_property PACKAGE_PIN T16 [get_ports {FPGA_IO_B[13]}]; # JX1_LVDS_8_P (34) +# set_property PACKAGE_PIN U17 [get_ports {FPGA_IO_B[14]}]; # JX1_LVDS_8_N (34) +# set_property PACKAGE_PIN U14 [get_ports {FPGA_IO_B[15]}]; # JX1_LVDS_10_P (34) +# set_property PACKAGE_PIN U15 [get_ports {FPGA_IO_B[16]}]; # JX1_LVDS_10_N (34) +# set_property PACKAGE_PIN T20 [get_ports {FPGA_IO_B[17]}]; # JX1_LVDS_14_P (34) +# set_property PACKAGE_PIN U20 [get_ports {FPGA_IO_B[18]}]; # JX1_LVDS_14_N (34) +# set_property PACKAGE_PIN Y18 [get_ports {FPGA_IO_B[19]}]; # JX1_LVDS_16_P (34) +# set_property PACKAGE_PIN Y19 [get_ports {FPGA_IO_B[20]}]; # JX1_LVDS_16_N (34) +# set_property PACKAGE_PIN R16 [get_ports {FPGA_IO_B[21]}]; # JX1_LVDS_18_P (34) +# set_property PACKAGE_PIN R17 [get_ports {FPGA_IO_B[22]}]; # JX1_LVDS_18_N (34) +set_property PACKAGE_PIN V17 [get_ports {IRC_IRQ_0}]; # PMOD1[6] JX1_LVDS_20_P (34) +# set_property PACKAGE_PIN V18 [get_ports {FPGA_IO_B[24]}]; # PMOD1[7] JX1_LVDS_20_N (34) +# set_property PACKAGE_PIN N17 [get_ports {FPGA_IO_B[25]}]; # PMOD1[4] JX1_LVDS_22_P (34) +# set_property PACKAGE_PIN P18 [get_ports {FPGA_IO_B[26]}]; # PMOD1[5] JX1_LVDS_22_N (34) +set_property PACKAGE_PIN P15 [get_ports {IRC_A_1}]; # PMOD2[2] JX1_LVDS_23_P (34) +set_property PACKAGE_PIN P16 [get_ports {IRC_B_1}]; # PMOD2[3] JX1_LVDS_23_N (34) + +set_property PACKAGE_PIN W18 [get_ports {PWM_A_1}]; # PMOD2[0] JX1_LVDS_21_P (34) +set_property PACKAGE_PIN W19 [get_ports {PWM_B_1}]; # PMOD2[1] JX1_LVDS_21_N (34) +# set_property PACKAGE_PIN T17 [get_ports {FPGA_IO_C[33]}]; # PMOD2[4] JX1_LVDS_19_P (34) +# set_property PACKAGE_PIN R18 [get_ports {FPGA_IO_C[34]}]; # PMOD2[5] JX1_LVDS_19_N (34) +set_property PACKAGE_PIN V16 [get_ports {IRC_IRQ_1}]; # PMOD2[6] JX1_LVDS_17_P (34) +# set_property PACKAGE_PIN W16 [get_ports {FPGA_IO_C[36]}]; # PMOD2[7] JX1_LVDS_17_N (34) +set_property PACKAGE_PIN V20 [get_ports {IRC_A_0}]; # PMOD1[2] JX1_LVDS_15_P (34) +set_property PACKAGE_PIN W20 [get_ports {IRC_B_0}]; # PMOD1[3] JX1_LVDS_15_N (34) +set_property PACKAGE_PIN N20 [get_ports {PWM_A_0}]; # PMOD1[0] JX1_LVDS_13_P (34) +set_property PACKAGE_PIN P20 [get_ports {PWM_B_0}]; # PMOD1[1] JX1_LVDS_13_N (34) # ------------------------------------------------------------------------------ # Camera 1 pins diff --git a/system/src/top/top.bd b/system/src/top/top.bd index 826baa0..479ce36 100644 --- a/system/src/top/top.bd +++ b/system/src/top/top.bd @@ -1,4964 +1,3254 @@ - - - - - xilinx.com - BlockDiagram - top - 1.00.a - - - isTop - true - - - - - DDR - - - - - - TIMEPERIOD_PS - 1250 - - - - - - - - MEMORY_TYPE - COMPONENTS - - - - - - - - DATA_WIDTH - 8 - - - - - - - - CS_ENABLED - true - - - - - - - - DATA_MASK_ENABLED - true - - - - - - - - SLOT - Single - - - - - - - - MEM_ADDR_MAP - ROW_COLUMN_BANK - - - - - - - - BURST_LENGTH - 8 - - - - - - - - AXI_ARBITRATION_SCHEME - TDM - - - - - - - - CAS_LATENCY - 11 - - - - - - - - CAS_WRITE_LATENCY - 11 - - - - - - - - - - FIXED_IO - - - - - - DATA.LCD_D - Data - Data - - - - - - - DATA - - - LCD_D - - - - - - LAYERED_METADATA - undef - - - - - - - - - - - - - BlockDiagram - :vivado.xilinx.com: - - - - - - ENCDATA - - in - - - - RESET - - out - - - - LEDCLK - - out - - - - LEDCS - - out - - - - LEDDATA - - out - - - - SERVO1 - - out - - - - SERVO2 - - out - - - - SERVO3 - - out - - - - SERVO4 - - inout - - - - CAN1_TXD - - out - - - - CAN2_TXD - - out - - - - CAN1_RXD - - in - - - - CAN2_RXD - - in - - - - LCD_D - - inout - - 15 - 0 - - - - - LCD_RST - - out - - - - LCD_WR - - out - - - - LCD_RS - - out - - - - SPEAKER - - out - - - - LCD_CS - - out - - - - FPGA_IO_A - - inout - - 10 - 1 - - - - - FPGA_IO_B - - inout - - 28 - 13 - - - - - FPGA_IO_C - - inout - - 40 - 31 - - - - - - - - - xilinx.com - BlockDiagram - top_imp - 1.00.a - - - canbench_cc_gpio_0 - - - top_canbench_cc_gpio_0_0 - - - - processing_system7_0_axi_periph - - - top_processing_system7_0_axi_periph_0 - 7 - 0 - xilinx.com:ip:axi_interconnect:2.1 - - - - processing_system7_0 - - - top_processing_system7_0_0 - true - -0.073 - -0.072 - 0.024 - 0.023 - 0.294 - 0.298 - 0.338 - 0.334 - 50.05 - 50.43 - 50.10 - 50.01 - 49.59 - 51.74 - 50.32 - 48.55 - 39.7 - 39.7 - 54.14 - 54.14 - 33.333333 - 667 - 200 - 50 - 50 - 20 - 100 - 100 - 33.333333 - 50 - 533.333374 - 1 - 0 - 1 - 0 - 1 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 1 - LVCMOS 3.3V - LVCMOS 1.8V - DDR 3 (Low Voltage) - 32 Bit - 8 - MT41K256M16 RE-125 - 1 - 1 - 1 - 1 - 1 - 1 - MIO 1 .. 6 - 1 - MIO 8 - 1 - MIO 16 .. 27 - 1 - MIO 52 .. 53 - 0 - 1 - MIO 40 .. 45 - 1 - MIO 46 - 1 - MIO 50 - 1 - MIO 10 .. 11 - 1 - MIO 48 .. 49 - 1 - EMIO - 0 - 1 - EMIO - 1 - EMIO - 1 - MIO 28 .. 39 - 0 - 1 - 1 - 1 - 6:2:1 - 1000 Mbps - ARM PLL - DDR PLL - IO PLL - IO PLL - IO PLL - IO PLL - IO PLL - IO PLL - IO PLL - IO PLL - CPU_1X - CPU_1X - CPU_1X - disabled - slow - disabled - slow - slow - slow - slow - slow - slow - slow - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - disabled - slow - clg400 - - - - rst_processing_system7_0_100M - - - top_rst_processing_system7_0_100M_0 - - - - xlconcat_0 - - - top_xlconcat_0_0 - - - - axi_pwm_coprocessor_0 - - - top_axi_pwm_coprocessor_0_0 - - - - axi_mem_intercon - - - top_axi_mem_intercon_0 - 3 - 1 - xilinx.com:ip:axi_interconnect:2.1 - - - - servo_led_ps2_0 - - - top_servo_led_ps2_0_0 - - - - spi_leds_and_enc_0 - - - top_spi_leds_and_enc_0_0 - - - - audio_single_pwm_0 - - - top_audio_single_pwm_0_0 - - - - display_16bit_cmd_data_bus_0 - - - top_display_16bit_cmd_data_bus_0_0 - - - - dcsimpledrv_to_pmod12_pins_0 - - - top_dcsimpledrv_to_pmod12_pins_0_0 - - - - xlconcat_1 - - - top_xlconcat_1_0 - 8 - - - - dcsimpledrv_0 - - - top_dcsimpledrv_0_0 - - - - dcsimpledrv_1 - - - top_dcsimpledrv_1_0 - - - - - - processing_system7_0_M_AXI_GP0 - - - - - axi_pwm_coprocessor_0_M00_AXI - - - - - axi_mem_intercon_M00_AXI - - - - - processing_system7_0_axi_periph_M01_AXI - - - - - processing_system7_0_axi_periph_M04_AXI - - - - - processing_system7_0_axi_periph_M05_AXI - - - - - processing_system7_0_axi_periph_M06_AXI - - - - - audio_single_pwm_0_M00_AXI - - - - - processing_system7_0_axi_periph_M00_AXI - - - - - display_16bit_cmd_data_bus_0_M00_AXI - - - - - processing_system7_0_axi_periph_M02_AXI - - - - - processing_system7_0_axi_periph_M03_AXI - - - - - - - processing_system7_0_FCLK_CLK0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - processing_system7_0_FCLK_RESET0_N - - - - - rst_processing_system7_0_100M_peripheral_aresetn - - - - - - - - - - - - - - - - - - - - - - - - - - rst_processing_system7_0_100M_interconnect_aresetn - - - - - - canbench_cc_gpio_0_GPIO_I - - - - - processing_system7_0_GPIO_O - - - - - xlconcat_0_dout - - - - - ENCDATA_1 - - - - - spi_leds_and_enc_0_spi_led_reset - - - - - spi_leds_and_enc_0_spi_led_clk - - - - - spi_leds_and_enc_0_spi_led_cs - - - - - spi_leds_and_enc_0_spi_led_data - - - - - servo_led_ps2_0_SERVO1 - - - - - servo_led_ps2_0_SERVO2 - - - - - servo_led_ps2_0_SERVO3 - - - - - Net - - - - - audio_single_pwm_0_irq_rq_out - - - - - processing_system7_0_CAN0_PHY_TX - - - - - processing_system7_0_CAN1_PHY_TX - - - - - CAN1_RXD_1 - - - - - CAN2_RXD_1 - - - - - Net1 - - - - - display_16bit_cmd_data_bus_0_irq_rq_out - - - - - display_16bit_cmd_data_bus_0_lcd_res_n - - - - - display_16bit_cmd_data_bus_0_lcd_wr_n - - - - - display_16bit_cmd_data_bus_0_lcd_dc - - - - - audio_single_pwm_0_speaker_pwm_out - - - - - display_16bit_cmd_data_bus_0_lcd_cs_n - - - - - Net2 - - - - - Net3 - - - - - Net4 - - - - - dcsimpledrv_to_pmod12_pins_0_IRC1_A - - - - - dcsimpledrv_to_pmod12_pins_0_IRC1_B - - - - - dcsimpledrv_to_pmod12_pins_0_IRC1_IRQ - - - - - dcsimpledrv_0_PWM_A - - - - - dcsimpledrv_0_PWM_B - - - - - dcsimpledrv_1_PWM_A - - - - - dcsimpledrv_1_PWM_B - - - - - dcsimpledrv_to_pmod12_pins_0_IRC2_A - - - - - dcsimpledrv_to_pmod12_pins_0_IRC2_B - - - - - dcsimpledrv_to_pmod12_pins_0_IRC2_IRQ - - - - - dcsimpledrv_0_IRC_A_MON - - - - - dcsimpledrv_0_IRC_B_MON - - - - - dcsimpledrv_0_IRC_IRQ_MON - - - - - dcsimpledrv_0_IRC_CHG_MON - - - - - dcsimpledrv_1_IRC_A_MON - - - - - dcsimpledrv_1_IRC_B_MON - - - - - dcsimpledrv_1_IRC_IRQ_MON - - - - - dcsimpledrv_1_IRC_CHG_MON - - - - - xlconcat_1_dout - - - - - - - - - - - - - - - - xilinx.com - BlockDiagram/top_imp - axi_mem_intercon - 1.00.a - - - S00_AXI - - - - - - M00_AXI - - - - - - S01_AXI - - - - - - S02_AXI - - - - - - CLK.ACLK - Clk - Clock - - - - - - - CLK - - - ACLK - - - - - - RST.ARESETN - Reset - Reset - - - - - - - RST - - - ARESETN - - - - - - CLK.S00_ACLK - Clk - Clock - - - - - - - CLK - - - S00_ACLK - - - - - - ASSOCIATED_BUSIF - S00_AXI - - - - - - - - ASSOCIATED_RESET - S00_ARESETN - - - - - - - - - - RST.S00_ARESETN - Reset - Reset - - - - - - - RST - - - S00_ARESETN - - - - - - CLK.M00_ACLK - Clk - Clock - - - - - - - CLK - - - M00_ACLK - - - - - - ASSOCIATED_BUSIF - M00_AXI - - - - - - - - ASSOCIATED_RESET - M00_ARESETN - - - - - - - - - - RST.M00_ARESETN - Reset - Reset - - - - - - - RST - - - M00_ARESETN - - - - - - CLK.S01_ACLK - Clk - Clock - - - - - - - CLK - - - S01_ACLK - - - - - - ASSOCIATED_BUSIF - S01_AXI - - - - - - - - ASSOCIATED_RESET - S01_ARESETN - - - - - - - - - - RST.S01_ARESETN - Reset - Reset - - - - - - - RST - - - S01_ARESETN - - - - - - CLK.S02_ACLK - Clk - Clock - - - - - - - CLK - - - S02_ACLK - - - - - - ASSOCIATED_BUSIF - S02_AXI - - - - - - - - ASSOCIATED_RESET - S02_ARESETN - - - - - - - - - - RST.S02_ARESETN - Reset - Reset - - - - - - - RST - - - S02_ARESETN - - - - - - - - - BlockDiagram - :vivado.xilinx.com: - - - - - - ACLK - - in - - - - ARESETN - - in - - 0 - 0 - - - - - S00_ACLK - - in - - - - S00_ARESETN - - in - - 0 - 0 - - - - - M00_ACLK - - in - - - - M00_ARESETN - - in - - 0 - 0 - - - - - S01_ACLK - - in - - - - S01_ARESETN - - in - - 0 - 0 - - - - - S02_ACLK - - in - - - - S02_ARESETN - - in - - 0 - 0 - - - - - - - - - xilinx.com - BlockDiagram/top_imp - axi_mem_intercon_imp - 1.00.a - - - xbar - - - top_xbar_0 - 3 - 1 - 0 - - - - s00_couplers - - - - s01_couplers - - - - s02_couplers - - - - m00_couplers - - - - - - s00_couplers_to_xbar - - - - - s01_couplers_to_xbar - - - - - s02_couplers_to_xbar - - - - - xbar_to_m00_couplers - - - - - - - axi_mem_intercon_ACLK_net - - - - - - - - - axi_mem_intercon_ARESETN_net - - - - - - - - - S00_ACLK_1 - - - - - S00_ARESETN_1 - - - - - S01_ACLK_1 - - - - - S01_ARESETN_1 - - - - - S02_ACLK_1 - - - - - S02_ARESETN_1 - - - - - M00_ACLK_1 - - - - - M00_ARESETN_1 - - - - - - - - - - - - - - - - - - - - - - xilinx.com - BlockDiagram/top_imp/axi_mem_intercon_imp - m00_couplers - 1.00.a - - - M_AXI - - - - - - S_AXI - - - - - - CLK.M_ACLK - Clk - Clock - - - - - - - CLK - - - M_ACLK - - - - - - ASSOCIATED_BUSIF - M_AXI - - - - - - - - ASSOCIATED_RESET - M_ARESETN - - - - - - - - - - RST.M_ARESETN - Reset - Reset - - - - - - - RST - - - M_ARESETN - - - - - - CLK.S_ACLK - Clk - Clock - - - - - - - CLK - - - S_ACLK - - - - - - ASSOCIATED_BUSIF - S_AXI - - - - - - - - ASSOCIATED_RESET - S_ARESETN - - - - - - - - - - RST.S_ARESETN - Reset - Reset - - - - - - - RST - - - S_ARESETN - - - - - - - - - BlockDiagram - :vivado.xilinx.com: - - - - - - M_ACLK - - in - - - - M_ARESETN - - in - - 0 - 0 - - - - - S_ACLK - - in - - - - S_ARESETN - - in - - 0 - 0 - - - - - - - - - xilinx.com - BlockDiagram/top_imp/axi_mem_intercon_imp - m00_couplers_imp - 1.00.a - - - auto_pc - - - top_auto_pc_1 - AXI4LITE - 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- - - M_ARESETN - - in - - 0 - 0 - - - - - S_ACLK - - in - - - - S_ARESETN - - in - - 0 - 0 - - - - - - - - - xilinx.com - BlockDiagram/top_imp/processing_system7_0_axi_periph_imp - m01_couplers_imp - 1.00.a - - - - - - - - - - - xilinx.com - BlockDiagram/top_imp/processing_system7_0_axi_periph_imp - m00_couplers - 1.00.a - - - M_AXI - - - - - - S_AXI - - - - - - CLK.M_ACLK - Clk - Clock - - - - - - - CLK - - - M_ACLK - - - - - - ASSOCIATED_BUSIF - M_AXI - - - - - - - - ASSOCIATED_RESET - M_ARESETN - - - - - - - - - - RST.M_ARESETN - Reset - Reset - - - - - - - RST - - - M_ARESETN - - - - - - CLK.S_ACLK - Clk - Clock - - - - - - - CLK - - - S_ACLK - - - - - - ASSOCIATED_BUSIF - S_AXI - - - - - - - - ASSOCIATED_RESET - S_ARESETN - - - - - - - - - - RST.S_ARESETN - Reset - Reset - - - - - - - RST - - - S_ARESETN - - - - - - - - - BlockDiagram - :vivado.xilinx.com: - - - - - - M_ACLK - - in - - - - M_ARESETN - - in - - 0 - 0 - - - - - S_ACLK - - in - - - - S_ARESETN - - in - - 0 - 0 - - - - - - - - - xilinx.com - BlockDiagram/top_imp/processing_system7_0_axi_periph_imp - m00_couplers_imp - 1.00.a - - - - - - - - - - - xilinx.com - BlockDiagram/top_imp/processing_system7_0_axi_periph_imp - s00_couplers - 1.00.a - - - M_AXI - - - - - - S_AXI - - - - - - CLK.M_ACLK - Clk - Clock - - - - - - - CLK - - - M_ACLK - - - - - - ASSOCIATED_BUSIF - M_AXI - - - - - - - - ASSOCIATED_RESET - M_ARESETN - - - - - - - - - - RST.M_ARESETN - Reset - Reset - - - - - - - RST - - - M_ARESETN - - - - - - CLK.S_ACLK - Clk - Clock - - - - - - - CLK - - - S_ACLK - - - - - - ASSOCIATED_BUSIF - S_AXI - - - - - - - - ASSOCIATED_RESET - S_ARESETN - - - - - - - - - - RST.S_ARESETN - Reset - Reset - - - - - - - RST - - - S_ARESETN - - - - - - - - - BlockDiagram - :vivado.xilinx.com: - - - - - - M_ACLK - - in - - - - M_ARESETN - - in - - 0 - 0 - - - - - S_ACLK - - in - - - - S_ARESETN - - in - - 0 - 0 - - - - - - - - - xilinx.com - BlockDiagram/top_imp/processing_system7_0_axi_periph_imp - s00_couplers_imp - 1.00.a - - - auto_pc - - - top_auto_pc_0 - AXI3 - AXI4LITE - - - - - - - S_ACLK_1 - - - - - S_ARESETN_1 - - - - - - - - - - - - - - - - xilinx.com - Addressing/processing_system7_0 - processing_system7 - 5.5 - - - Data - 4G - 32 - - - SEG_axi_pwm_coprocessor_0_S00_AXI_reg - /axi_pwm_coprocessor_0/S00_AXI/S00_AXI_reg - 0x43C10000 - 4K - - - SEG_servo_led_ps2_0_S00_AXI_reg - /servo_led_ps2_0/S00_AXI/S00_AXI_reg - 0x43C50000 - 4K - - - SEG_spi_leds_and_enc_0_S00_AXI_reg - /spi_leds_and_enc_0/S00_AXI/S00_AXI_reg - 0x43C40000 - 4K - - - SEG_audio_single_pwm_0_S00_AXI_reg - /audio_single_pwm_0/S00_AXI/S00_AXI_reg - 0x43C60000 - 64K - - - SEG_display_16bit_cmd_data_bus_0_S00_AXI_reg - /display_16bit_cmd_data_bus_0/S00_AXI/S00_AXI_reg - 0x43C00000 - 64K - - - SEG_dcsimpledrv_0_S00_AXI_reg - /dcsimpledrv_0/S00_AXI/S00_AXI_reg - 0x43C20000 - 64K - - - SEG_dcsimpledrv_1_S00_AXI_reg - /dcsimpledrv_1/S00_AXI/S00_AXI_reg - 0x43C30000 - 64K - - - - - - - - user.org - Addressing/axi_pwm_coprocessor_0 - axi_pwm_coprocessor - 1.0 - - - M00_AXI - 4G - 32 - - - SEG_processing_system7_0_GP0_DDR_LOWOCM - /processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM - 0x00000000 - 1G - - - SEG_processing_system7_0_GP0_QSPI_LINEAR - /processing_system7_0/S_AXI_GP0/GP0_QSPI_LINEAR - 0xFC000000 - 16M - - - SEG_processing_system7_0_GP0_IOP - /processing_system7_0/S_AXI_GP0/GP0_IOP - 0xE0000000 - 4M - - - SEG_processing_system7_0_GP0_M_AXI_GP0 - /processing_system7_0/S_AXI_GP0/GP0_M_AXI_GP0 - 0x40000000 - 1G - - - - - - - - user.org - Addressing/audio_single_pwm_0 - audio_single_pwm - 1.0 - - - M00_AXI - 4G - 32 - - - SEG_processing_system7_0_GP0_DDR_LOWOCM - /processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM - 0x00000000 - 1G - - - SEG_processing_system7_0_GP0_QSPI_LINEAR - /processing_system7_0/S_AXI_GP0/GP0_QSPI_LINEAR - 0xFC000000 - 16M - - - SEG_processing_system7_0_GP0_IOP - /processing_system7_0/S_AXI_GP0/GP0_IOP - 0xE0000000 - 4M - - - SEG_processing_system7_0_GP0_M_AXI_GP0 - /processing_system7_0/S_AXI_GP0/GP0_M_AXI_GP0 - 0x40000000 - 1G - - - - - - - - user.org - Addressing/display_16bit_cmd_data_bus_0 - display_16bit_cmd_data_bus - 1.0 - - - M00_AXI - 4G - 32 - - - SEG_processing_system7_0_GP0_DDR_LOWOCM - /processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM - 0x00000000 - 1G - - - SEG_processing_system7_0_GP0_QSPI_LINEAR - /processing_system7_0/S_AXI_GP0/GP0_QSPI_LINEAR - 0xFC000000 - 16M - - - SEG_processing_system7_0_GP0_IOP - /processing_system7_0/S_AXI_GP0/GP0_IOP - 0xE0000000 - 4M - - - SEG_processing_system7_0_GP0_M_AXI_GP0 - /processing_system7_0/S_AXI_GP0/GP0_M_AXI_GP0 - 0x40000000 - 1G - - - - - - - +{ + "design": { + "design_info": { + "boundary_crc": "0xBFA0982DA5F37366", + "device": "xc7z010clg400-1", + "name": "top", + "synth_flow_mode": "Hierarchical", + "tool_version": "2019.1", + "validated": "true" + }, + "design_tree": { + "canbench_cc_gpio_0": "", + "processing_system7_0_axi_periph": { + "xbar": "", + "s00_couplers": { + "auto_pc": "" + }, + "m00_couplers": {}, + "m01_couplers": {}, + "m02_couplers": {}, + "m03_couplers": {}, + "m04_couplers": {}, + "m05_couplers": {}, + "m06_couplers": {} + }, + "processing_system7_0": "", + "rst_processing_system7_0_100M": "", + "xlconcat_0": "", + "axi_pwm_coprocessor_0": "", + "axi_mem_intercon": { + "xbar": "", + "s00_couplers": {}, + "s01_couplers": {}, + "s02_couplers": {}, + "m00_couplers": { + "auto_pc": "" + } + }, + "servo_led_ps2_0": "", + "spi_leds_and_enc_0": "", + "audio_single_pwm_0": "", + "display_16bit_cmd_data_bus_0": "", + "xlconcat_1": "", + "dcsimpledrv_0": "", + "dcsimpledrv_1": "" + }, + "interface_ports": { + "DDR": { + "mode": "Master", + "vlnv": "xilinx.com:interface:ddrx_rtl:1.0", + "parameters": { + "AXI_ARBITRATION_SCHEME": { + "value": "TDM", + "value_src": "default" + }, + "BURST_LENGTH": { + "value": "8", + "value_src": "default" + }, + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + }, + "CAS_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CAS_WRITE_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CS_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_MASK_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_WIDTH": { + "value": "8", + "value_src": "default" + }, + "MEMORY_TYPE": { + "value": "COMPONENTS", + "value_src": "default" + }, + "MEM_ADDR_MAP": { + "value": "ROW_COLUMN_BANK", + "value_src": "default" + }, + "SLOT": { + "value": "Single", + "value_src": "default" + }, + "TIMEPERIOD_PS": { + "value": "1250", + "value_src": "default" + } + } + }, + "FIXED_IO": { + "mode": "Master", + "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0", + "parameters": { + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + } + } + } + }, + "ports": { + "ENCDATA": { + "direction": "I" + }, + "RESET": { + "direction": "O" + }, + "LEDCLK": { + "direction": "O" + }, + "LEDCS": { + "direction": "O" + }, + "LEDDATA": { + "direction": "O" + }, + "SERVO1": { + "direction": "O" + }, + "SERVO2": { + "direction": "O" + }, + "SERVO3": { + "direction": "O" + }, + "SERVO4": { + "direction": "IO" + }, + "CAN1_TXD": { + "direction": "O" + }, + "CAN2_TXD": { + "direction": "O" + }, + "CAN1_RXD": { + "direction": "I" + }, + "CAN2_RXD": { + "direction": "I" + }, + "LCD_D": { + "type": "data", + "direction": "IO", + "left": "15", + "right": "0", + "parameters": { + "LAYERED_METADATA": { + "value": "undef", + "value_src": "default" + } + } + }, + "LCD_RST": { + "direction": "O" + }, + "LCD_WR": { + "direction": "O" + }, + "LCD_RS": { + "direction": "O" + }, + "SPEAKER": { + "direction": "O" + }, + "LCD_CS": { + "direction": "O" + }, + "PWM_A_0": { + "direction": "O" + }, + "PWM_B_0": { + "direction": "O" + }, + "IRC_IRQ_0": { + "direction": "I" + }, + "IRC_B_0": { + "direction": "I" + }, + "IRC_A_0": { + "direction": "I" + }, + "IRC_A_1": { + "direction": "I" + }, + "IRC_B_1": { + "direction": "I" + }, + "IRC_IRQ_1": { + "direction": "I" + }, + "PWM_B_1": { + "direction": "O" + }, + "PWM_A_1": { + "direction": "O" + } + }, + "components": { + "canbench_cc_gpio_0": { + "vlnv": "user.org:user:canbench_cc_gpio:1.0", + "xci_name": "top_canbench_cc_gpio_0_0" + }, + "processing_system7_0_axi_periph": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_name": "top_processing_system7_0_axi_periph_0", + "parameters": { + "ENABLE_ADVANCED_OPTIONS": { + "value": "0" + }, + "NUM_MI": { + "value": "7" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M01_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M02_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M03_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M04_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M05_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M06_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I" + }, + "ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + }, + "M01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M01_ARESETN" + } + } + }, + "M01_ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + }, + "M02_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M02_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M02_ARESETN" + } + } + }, + "M02_ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + }, + "M03_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M03_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M03_ARESETN" + } + } + }, + "M03_ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + }, + "M04_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M04_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M04_ARESETN" + } + } + }, + "M04_ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + }, + "M05_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M05_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M05_ARESETN" + } + } + }, + "M05_ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + }, + "M06_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M06_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M06_ARESETN" + } + } + }, + "M06_ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "top_xbar_0", + "parameters": { + "NUM_MI": { + "value": "7" + }, + "NUM_SI": { + "value": "1" + }, + "STRATEGY": { + "value": "0" + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_pc": { + "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", + "xci_name": "top_auto_pc_0", + "parameters": { + "MI_PROTOCOL": { + "value": "AXI4LITE" + }, + "SI_PROTOCOL": { + "value": "AXI3" + } + } + } + }, + "interface_nets": { + "auto_pc_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] + }, + "s00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_pc/aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_pc/aresetn" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m00_couplers_to_m00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m01_couplers_to_m01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m02_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m02_couplers_to_m02_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m03_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m03_couplers_to_m03_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m04_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m04_couplers_to_m04_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m05_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m05_couplers_to_m05_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m06_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m06_couplers_to_m06_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "processing_system7_0_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "xbar_to_m02_couplers": { + "interface_ports": [ + "xbar/M02_AXI", + "m02_couplers/S_AXI" + ] + }, + "xbar_to_m05_couplers": { + "interface_ports": [ + "xbar/M05_AXI", + "m05_couplers/S_AXI" + ] + }, + "m06_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M06_AXI", + "m06_couplers/M_AXI" + ] + }, + "xbar_to_m06_couplers": { + "interface_ports": [ + "xbar/M06_AXI", + "m06_couplers/S_AXI" + ] + }, + "xbar_to_m04_couplers": { + "interface_ports": [ + "xbar/M04_AXI", + "m04_couplers/S_AXI" + ] + }, + "m04_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M04_AXI", + "m04_couplers/M_AXI" + ] + }, + "m03_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M03_AXI", + "m03_couplers/M_AXI" + ] + }, + "m02_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M02_AXI", + "m02_couplers/M_AXI" + ] + }, + "m00_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M00_AXI", + "m00_couplers/M_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "m01_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M01_AXI", + "m01_couplers/M_AXI" + ] + }, + "xbar_to_m01_couplers": { + "interface_ports": [ + "xbar/M01_AXI", + "m01_couplers/S_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "m05_couplers_to_processing_system7_0_axi_periph": { + "interface_ports": [ + "M05_AXI", + "m05_couplers/M_AXI" + ] + }, + "xbar_to_m03_couplers": { + "interface_ports": [ + "xbar/M03_AXI", + "m03_couplers/S_AXI" + ] + } + }, + "nets": { + "processing_system7_0_axi_periph_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/M_ACLK", + "m00_couplers/S_ACLK", + "m01_couplers/S_ACLK", + "m02_couplers/S_ACLK", + "m03_couplers/S_ACLK", + "m04_couplers/S_ACLK", + "m05_couplers/S_ACLK", + "m06_couplers/S_ACLK" + ] + }, + "processing_system7_0_axi_periph_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/M_ARESETN", + "m00_couplers/S_ARESETN", + "m01_couplers/S_ARESETN", + "m02_couplers/S_ARESETN", + "m03_couplers/S_ARESETN", + "m04_couplers/S_ARESETN", + "m05_couplers/S_ARESETN", + "m06_couplers/S_ARESETN" + ] + }, + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "M00_ACLK_1": { + "ports": [ + "M00_ACLK", + "m00_couplers/M_ACLK" + ] + }, + "M00_ARESETN_1": { + "ports": [ + "M00_ARESETN", + "m00_couplers/M_ARESETN" + ] + }, + "M01_ACLK_1": { + "ports": [ + "M01_ACLK", + "m01_couplers/M_ACLK" + ] + }, + "M01_ARESETN_1": { + "ports": [ + "M01_ARESETN", + "m01_couplers/M_ARESETN" + ] + }, + "M02_ACLK_1": { + "ports": [ + "M02_ACLK", + "m02_couplers/M_ACLK" + ] + }, + "M02_ARESETN_1": { + "ports": [ + "M02_ARESETN", + "m02_couplers/M_ARESETN" + ] + }, + "M03_ACLK_1": { + "ports": [ + "M03_ACLK", + "m03_couplers/M_ACLK" + ] + }, + "M03_ARESETN_1": { + "ports": [ + "M03_ARESETN", + "m03_couplers/M_ARESETN" + ] + }, + "M04_ACLK_1": { + "ports": [ + "M04_ACLK", + "m04_couplers/M_ACLK" + ] + }, + "M04_ARESETN_1": { + "ports": [ + "M04_ARESETN", + "m04_couplers/M_ARESETN" + ] + }, + "M05_ACLK_1": { + "ports": [ + "M05_ACLK", + "m05_couplers/M_ACLK" + ] + }, + "M05_ARESETN_1": { + "ports": [ + "M05_ARESETN", + "m05_couplers/M_ARESETN" + ] + }, + "M06_ACLK_1": { + "ports": [ + "M06_ACLK", + "m06_couplers/M_ACLK" + ] + }, + "M06_ARESETN_1": { + "ports": [ + "M06_ARESETN", + "m06_couplers/M_ARESETN" + ] + } + } + }, + "processing_system7_0": { + "vlnv": "xilinx.com:ip:processing_system7:5.5", + "xci_name": "top_processing_system7_0_0", + "parameters": { + "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { + "value": "666.666687" + }, + "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { + "value": "20.000000" + }, + "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.158730" + }, + "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": { + "value": "125.000000" + }, + "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": { + "value": "50.000000" + }, + "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_UART_PERIPHERAL_FREQMHZ": { + "value": "50.000000" + }, + "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_APU_CLK_RATIO_ENABLE": { + "value": "6:2:1" + }, + "PCW_APU_PERIPHERAL_FREQMHZ": { + "value": "667" + }, + "PCW_CAN0_CAN0_IO": { + "value": "EMIO" + }, + "PCW_CAN0_GRP_CLK_ENABLE": { + "value": "0" + }, + "PCW_CAN0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_CAN1_CAN1_IO": { + "value": "EMIO" + }, + "PCW_CAN1_GRP_CLK_ENABLE": { + "value": "0" + }, + "PCW_CAN1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_CAN_PERIPHERAL_FREQMHZ": { + "value": "20" + }, + "PCW_CAN_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_CLK0_FREQ": { + "value": "100000000" + }, + "PCW_CLK1_FREQ": { + "value": "10000000" + }, + "PCW_CLK2_FREQ": { + "value": "10000000" + }, + "PCW_CLK3_FREQ": { + "value": "10000000" + }, + "PCW_CPU_CPU_6X4X_MAX_RANGE": { + "value": "667" + }, + "PCW_CPU_PERIPHERAL_CLKSRC": { + "value": "ARM PLL" + }, + "PCW_CRYSTAL_PERIPHERAL_FREQMHZ": { + "value": "33.333333" + }, + "PCW_DDR_PERIPHERAL_CLKSRC": { + "value": "DDR PLL" + }, + "PCW_DDR_RAM_HIGHADDR": { + "value": "0x3FFFFFFF" + }, + "PCW_DM_WIDTH": { + "value": "4" + }, + "PCW_DQS_WIDTH": { + "value": "4" + }, + "PCW_DQ_WIDTH": { + "value": "32" + }, + "PCW_ENET0_ENET0_IO": { + "value": "MIO 16 .. 27" + }, + "PCW_ENET0_GRP_MDIO_ENABLE": { + "value": "1" + }, + "PCW_ENET0_GRP_MDIO_IO": { + "value": "MIO 52 .. 53" + }, + "PCW_ENET0_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_ENET0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_ENET0_PERIPHERAL_FREQMHZ": { + "value": "1000 Mbps" + }, + "PCW_ENET0_RESET_ENABLE": { + "value": "0" + }, + "PCW_ENET_RESET_ENABLE": { + "value": "1" + }, + "PCW_ENET_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_EN_CAN0": { + "value": "1" + }, + "PCW_EN_CAN1": { + "value": "1" + }, + "PCW_EN_CLK0_PORT": { + "value": "1" + }, + "PCW_EN_CLK1_PORT": { + "value": "0" + }, + "PCW_EN_CLK2_PORT": { + "value": "0" + }, + "PCW_EN_CLK3_PORT": { + "value": "0" + }, + "PCW_EN_DDR": { + "value": "1" + }, + "PCW_EN_EMIO_CAN0": { + "value": "1" + }, + "PCW_EN_EMIO_CAN1": { + "value": "1" + }, + "PCW_EN_EMIO_GPIO": { + "value": "1" + }, + "PCW_EN_EMIO_TTC0": { + "value": "1" + }, + "PCW_EN_EMIO_UART0": { + "value": "0" + }, + "PCW_EN_ENET0": { + "value": "1" + }, + "PCW_EN_GPIO": { + "value": "1" + }, + "PCW_EN_QSPI": { + "value": "1" + }, + "PCW_EN_RST0_PORT": { + "value": "1" + }, + "PCW_EN_RST1_PORT": { + "value": "0" + }, + "PCW_EN_RST2_PORT": { + "value": "0" + }, + "PCW_EN_RST3_PORT": { + "value": "0" + }, + "PCW_EN_SDIO0": { + "value": "1" + }, + "PCW_EN_TTC0": { + "value": "1" + }, + "PCW_EN_UART0": { + "value": "1" + }, + "PCW_EN_UART1": { + "value": "1" + }, + "PCW_EN_USB0": { + "value": "1" + }, + "PCW_FCLK0_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK1_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK2_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK3_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK_CLK0_BUF": { + "value": "TRUE" + }, + "PCW_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "33.333333" + }, + "PCW_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_FPGA_FCLK0_ENABLE": { + "value": "1" + }, + "PCW_GPIO_EMIO_GPIO_ENABLE": { + "value": "1" + }, + "PCW_GPIO_EMIO_GPIO_IO": { + "value": "64" + }, + "PCW_GPIO_EMIO_GPIO_WIDTH": { + "value": "64" + }, + "PCW_GPIO_MIO_GPIO_ENABLE": { + "value": "1" + }, + "PCW_GPIO_MIO_GPIO_IO": { + "value": "MIO" + }, + "PCW_GPIO_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_I2C_RESET_ENABLE": { + "value": "0" + }, + "PCW_IRQ_F2P_INTR": { + "value": "1" + }, + "PCW_MIO_0_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_0_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_0_SLEW": { + "value": "slow" + }, + "PCW_MIO_10_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_10_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_10_SLEW": { + "value": "slow" + }, + "PCW_MIO_11_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_11_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_11_SLEW": { + "value": "slow" + }, + "PCW_MIO_12_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_12_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_12_SLEW": { + "value": "slow" + }, + "PCW_MIO_13_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_13_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_13_SLEW": { + "value": "slow" + }, + "PCW_MIO_14_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_14_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_14_SLEW": { + "value": "slow" + }, + "PCW_MIO_15_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_15_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_15_SLEW": { + "value": "slow" + }, + "PCW_MIO_16_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_16_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_16_SLEW": { + "value": "slow" + }, + "PCW_MIO_17_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_17_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_17_SLEW": { + "value": "slow" + }, + "PCW_MIO_18_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_18_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_18_SLEW": { + "value": "slow" + }, + "PCW_MIO_19_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_19_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_19_SLEW": { + "value": "slow" + }, + "PCW_MIO_1_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_1_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_1_SLEW": { + "value": "slow" + }, + "PCW_MIO_20_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_20_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_20_SLEW": { + "value": "slow" + }, + "PCW_MIO_21_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_21_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_21_SLEW": { + "value": "slow" + }, + "PCW_MIO_22_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_22_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_22_SLEW": { + "value": "slow" + }, + "PCW_MIO_23_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_23_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_23_SLEW": { + "value": "slow" + }, + "PCW_MIO_24_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_24_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_24_SLEW": { + "value": "slow" + }, + "PCW_MIO_25_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_25_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_25_SLEW": { + "value": "slow" + }, + "PCW_MIO_26_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_26_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_26_SLEW": { + "value": "slow" + }, + "PCW_MIO_27_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_27_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_27_SLEW": { + "value": "slow" + }, + "PCW_MIO_28_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_28_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_28_SLEW": { + "value": "slow" + }, + "PCW_MIO_29_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_29_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_29_SLEW": { + "value": "slow" + }, + "PCW_MIO_2_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_2_SLEW": { + "value": "slow" + }, + "PCW_MIO_30_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_30_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_30_SLEW": { + "value": "slow" + }, + "PCW_MIO_31_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_31_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_31_SLEW": { + "value": "slow" + }, + "PCW_MIO_32_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_32_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_32_SLEW": { + "value": "slow" + }, + "PCW_MIO_33_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_33_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_33_SLEW": { + "value": "slow" + }, + "PCW_MIO_34_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_34_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_34_SLEW": { + "value": "slow" + }, + "PCW_MIO_35_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_35_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_35_SLEW": { + "value": "slow" + }, + "PCW_MIO_36_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_36_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_36_SLEW": { + "value": "slow" + }, + "PCW_MIO_37_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_37_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_37_SLEW": { + "value": "slow" + }, + "PCW_MIO_38_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_38_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_38_SLEW": { + "value": "slow" + }, + "PCW_MIO_39_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_39_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_39_SLEW": { + "value": "slow" + }, + "PCW_MIO_3_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_3_SLEW": { + "value": "slow" + }, + "PCW_MIO_40_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_40_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_40_SLEW": { + "value": "slow" + }, + "PCW_MIO_41_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_41_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_41_SLEW": { + "value": "slow" + }, + "PCW_MIO_42_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_42_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_42_SLEW": { + "value": "slow" + }, + "PCW_MIO_43_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_43_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_43_SLEW": { + "value": "slow" + }, + "PCW_MIO_44_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_44_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_44_SLEW": { + "value": "slow" + }, + "PCW_MIO_45_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_45_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_45_SLEW": { + "value": "slow" + }, + "PCW_MIO_46_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_46_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_46_SLEW": { + "value": "slow" + }, + "PCW_MIO_47_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_47_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_47_SLEW": { + "value": "slow" + }, + "PCW_MIO_48_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_48_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_48_SLEW": { + "value": "slow" + }, + "PCW_MIO_49_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_49_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_49_SLEW": { + "value": "slow" + }, + "PCW_MIO_4_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_4_SLEW": { + "value": "slow" + }, + "PCW_MIO_50_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_50_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_50_SLEW": { + "value": "slow" + }, + "PCW_MIO_51_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_51_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_51_SLEW": { + "value": "slow" + }, + "PCW_MIO_52_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_52_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_52_SLEW": { + "value": "slow" + }, + "PCW_MIO_53_IOTYPE": { + "value": "LVCMOS 1.8V" + }, + "PCW_MIO_53_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_53_SLEW": { + "value": "slow" + }, + "PCW_MIO_5_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_5_SLEW": { + "value": "slow" + }, + "PCW_MIO_6_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_6_SLEW": { + "value": "slow" + }, + "PCW_MIO_7_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_7_SLEW": { + "value": "slow" + }, + "PCW_MIO_8_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_8_SLEW": { + "value": "slow" + }, + "PCW_MIO_9_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_9_PULLUP": { + "value": "disabled" + }, + "PCW_MIO_9_SLEW": { + "value": "slow" + }, + "PCW_MIO_PRIMITIVE": { + "value": "54" + }, + "PCW_MIO_TREE_PERIPHERALS": { + "value": "GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#UART 0#UART 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#UART 1#UART 1#SD 0#GPIO#Enet 0#Enet 0" + }, + "PCW_MIO_TREE_SIGNALS": { + "value": "gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#rx#tx#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#cd#gpio[47]#tx#rx#wp#gpio[51]#mdc#mdio" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY0": { + "value": "0.361" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY1": { + "value": "0.351" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY2": { + "value": "0.386" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY3": { + "value": "0.391" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0": { + "value": "-0.112" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1": { + "value": "-0.093" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2": { + "value": "0.019" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3": { + "value": "0.009" + }, + "PCW_PACKAGE_NAME": { + "value": "clg400" + }, + "PCW_PRESET_BANK0_VOLTAGE": { + "value": "LVCMOS 3.3V" + }, + "PCW_PRESET_BANK1_VOLTAGE": { + "value": "LVCMOS 1.8V" + }, + "PCW_QSPI_GRP_FBCLK_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_FBCLK_IO": { + "value": "MIO 8" + }, + "PCW_QSPI_GRP_IO1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_GRP_SINGLE_SS_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_SINGLE_SS_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_QSPI_GRP_SS1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_QSPI_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_QSPI_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_QSPI_QSPI_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_SD0_GRP_CD_ENABLE": { + "value": "1" + }, + "PCW_SD0_GRP_CD_IO": { + "value": "MIO 46" + }, + "PCW_SD0_GRP_POW_ENABLE": { + "value": "0" + }, + "PCW_SD0_GRP_WP_ENABLE": { + "value": "1" + }, + "PCW_SD0_GRP_WP_IO": { + "value": "MIO 50" + }, + "PCW_SD0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_SD0_SD0_IO": { + "value": "MIO 40 .. 45" + }, + "PCW_SDIO_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SDIO_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_SDIO_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_SINGLE_QSPI_DATA_MODE": { + "value": "x4" + }, + "PCW_TTC0_CLK0_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC0_CLK1_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC0_CLK2_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_TTC0_TTC0_IO": { + "value": "EMIO" + }, + "PCW_TTC_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_UART0_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART0_UART0_IO": { + "value": "MIO 10 .. 11" + }, + "PCW_UART1_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART1_UART1_IO": { + "value": "MIO 48 .. 49" + }, + "PCW_UART_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_UART_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_UART_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": { + "value": "533.333374" + }, + "PCW_UIPARAM_DDR_BL": { + "value": "8" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY0": { + "value": "0.294" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY1": { + "value": "0.298" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY2": { + "value": "0.338" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY3": { + "value": "0.334" + }, + "PCW_UIPARAM_DDR_BUS_WIDTH": { + "value": "32 Bit" + }, + "PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM": { + "value": "39.7" + }, + "PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM": { + "value": "39.7" + }, + "PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM": { + "value": "54.14" + }, + "PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM": { + "value": "54.14" + }, + "PCW_UIPARAM_DDR_DQS_0_LENGTH_MM": { + "value": "50.05" + }, + "PCW_UIPARAM_DDR_DQS_1_LENGTH_MM": { + "value": "50.43" + }, + "PCW_UIPARAM_DDR_DQS_2_LENGTH_MM": { + "value": "50.10" + }, + "PCW_UIPARAM_DDR_DQS_3_LENGTH_MM": { + "value": "50.01" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0": { + "value": "-0.073" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1": { + "value": "-0.072" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2": { + "value": "0.024" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3": { + "value": "0.023" + }, + "PCW_UIPARAM_DDR_DQ_0_LENGTH_MM": { + "value": "49.59" + }, + "PCW_UIPARAM_DDR_DQ_1_LENGTH_MM": { + "value": "51.74" + }, + "PCW_UIPARAM_DDR_DQ_2_LENGTH_MM": { + "value": "50.32" + }, + "PCW_UIPARAM_DDR_DQ_3_LENGTH_MM": { + "value": "48.55" + }, + "PCW_UIPARAM_DDR_MEMORY_TYPE": { + "value": "DDR 3 (Low Voltage)" + }, + "PCW_UIPARAM_DDR_PARTNO": { + "value": "MT41K256M16 RE-125" + }, + "PCW_UIPARAM_DDR_TRAIN_DATA_EYE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_TRAIN_READ_GATE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL": { + "value": "1" + }, + "PCW_UIPARAM_DDR_USE_INTERNAL_VREF": { + "value": "1" + }, + "PCW_USB0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_USB0_RESET_ENABLE": { + "value": "0" + }, + "PCW_USB0_USB0_IO": { + "value": "MIO 28 .. 39" + }, + "PCW_USB_RESET_ENABLE": { + "value": "1" + }, + "PCW_USB_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_USE_CROSS_TRIGGER": { + "value": "0" + }, + "PCW_USE_FABRIC_INTERRUPT": { + "value": "1" + }, + "PCW_USE_M_AXI_GP0": { + "value": "1" + }, + "PCW_USE_M_AXI_GP1": { + "value": "0" + }, + "PCW_USE_S_AXI_GP0": { + "value": "1" + } + } + }, + "rst_processing_system7_0_100M": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "top_rst_processing_system7_0_100M_0" + }, + "xlconcat_0": { + "vlnv": "xilinx.com:ip:xlconcat:2.1", + "xci_name": "top_xlconcat_0_0" + }, + "axi_pwm_coprocessor_0": { + "vlnv": "user.org:user:axi_pwm_coprocessor:1.0", + "xci_name": "top_axi_pwm_coprocessor_0_0" + }, + "axi_mem_intercon": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_name": "top_axi_mem_intercon_0", + "parameters": { + "NUM_MI": { + "value": "1" + }, + "NUM_SI": { + "value": "3" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S01_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S02_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I" + }, + "ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + }, + "S01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S01_ARESETN" + } + } + }, + "S01_ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + }, + "S02_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S02_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S02_ARESETN" + } + } + }, + "S02_ARESETN": { + "type": "rst", + "direction": "I", + "left": "0", + "right": "0" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "top_xbar_1", + "parameters": { + "NUM_MI": { + "value": "1" + }, + "NUM_SI": { + "value": "3" + }, + "STRATEGY": { + "value": "0" + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "s00_couplers_to_s00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "s01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "s01_couplers_to_s01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "s02_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "s02_couplers_to_s02_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_pc": { + "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", + "xci_name": "top_auto_pc_1", + "parameters": { + "MI_PROTOCOL": { + "value": "AXI3" + }, + "SI_PROTOCOL": { + "value": "AXI4LITE" + } + } + } + }, + "interface_nets": { + "auto_pc_to_m00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] + }, + "m00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_pc/aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_pc/aresetn" + ] + } + } + } + }, + "interface_nets": { + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "s02_couplers_to_xbar": { + "interface_ports": [ + "s02_couplers/M_AXI", + "xbar/S02_AXI" + ] + }, + "axi_mem_intercon_to_s02_couplers": { + "interface_ports": [ + "S02_AXI", + "s02_couplers/S_AXI" + ] + }, + "axi_mem_intercon_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "s01_couplers_to_xbar": { + "interface_ports": [ + "s01_couplers/M_AXI", + "xbar/S01_AXI" + ] + }, + "axi_mem_intercon_to_s01_couplers": { + "interface_ports": [ + "S01_AXI", + "s01_couplers/S_AXI" + ] + }, + "m00_couplers_to_axi_mem_intercon": { + "interface_ports": [ + "M00_AXI", + "m00_couplers/M_AXI" + ] + } + }, + "nets": { + "axi_mem_intercon_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/M_ACLK", + "s01_couplers/M_ACLK", + "s02_couplers/M_ACLK", + "m00_couplers/S_ACLK" + ] + }, + "axi_mem_intercon_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/M_ARESETN", + "s01_couplers/M_ARESETN", + "s02_couplers/M_ARESETN", + "m00_couplers/S_ARESETN" + ] + }, + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "S01_ACLK_1": { + "ports": [ + "S01_ACLK", + "s01_couplers/S_ACLK" + ] + }, + "S01_ARESETN_1": { + "ports": [ + "S01_ARESETN", + "s01_couplers/S_ARESETN" + ] + }, + "S02_ACLK_1": { + "ports": [ + "S02_ACLK", + "s02_couplers/S_ACLK" + ] + }, + "S02_ARESETN_1": { + "ports": [ + "S02_ARESETN", + "s02_couplers/S_ARESETN" + ] + }, + "M00_ACLK_1": { + "ports": [ + "M00_ACLK", + "m00_couplers/M_ACLK" + ] + }, + "M00_ARESETN_1": { + "ports": [ + "M00_ARESETN", + "m00_couplers/M_ARESETN" + ] + } + } + }, + "servo_led_ps2_0": { + "vlnv": "user.org:user:servo_led_ps2:1.0", + "xci_name": "top_servo_led_ps2_0_0" + }, + "spi_leds_and_enc_0": { + "vlnv": "user.org:user:spi_leds_and_enc:1.0", + "xci_name": "top_spi_leds_and_enc_0_0" + }, + "audio_single_pwm_0": { + "vlnv": "user.org:user:audio_single_pwm:1.0", + "xci_name": "top_audio_single_pwm_0_0" + }, + "display_16bit_cmd_data_bus_0": { + "vlnv": "user.org:user:display_16bit_cmd_data_bus:1.0", + "xci_name": "top_display_16bit_cmd_data_bus_0_0" + }, + "xlconcat_1": { + "vlnv": "xilinx.com:ip:xlconcat:2.1", + "xci_name": "top_xlconcat_1_0", + "parameters": { + "NUM_PORTS": { + "value": "8" + } + } + }, + "dcsimpledrv_0": { + "vlnv": "pikron.com:user:dcsimpledrv:1.0", + "xci_name": "top_dcsimpledrv_0_0" + }, + "dcsimpledrv_1": { + "vlnv": "pikron.com:user:dcsimpledrv:1.0", + "xci_name": "top_dcsimpledrv_1_0" + } + }, + "interface_nets": { + "processing_system7_0_axi_periph_M05_AXI": { + "interface_ports": [ + "processing_system7_0_axi_periph/M05_AXI", + "servo_led_ps2_0/S00_AXI" + ] + }, + "processing_system7_0_DDR": { + "interface_ports": [ + "DDR", + "processing_system7_0/DDR" + ] + }, + "processing_system7_0_axi_periph_M06_AXI": { + "interface_ports": [ + "processing_system7_0_axi_periph/M06_AXI", + "audio_single_pwm_0/S00_AXI" + ] + }, + "processing_system7_0_axi_periph_M00_AXI": { + "interface_ports": [ + "processing_system7_0_axi_periph/M00_AXI", + "display_16bit_cmd_data_bus_0/S00_AXI" + ] + }, + "axi_mem_intercon_M00_AXI": { + "interface_ports": [ + "axi_mem_intercon/M00_AXI", + "processing_system7_0/S_AXI_GP0" + ] + }, + "axi_pwm_coprocessor_0_M00_AXI": { + "interface_ports": [ + "axi_pwm_coprocessor_0/M00_AXI", + "axi_mem_intercon/S00_AXI" + ] + }, + "processing_system7_0_axi_periph_M01_AXI": { + "interface_ports": [ + "processing_system7_0_axi_periph/M01_AXI", + "axi_pwm_coprocessor_0/S00_AXI" + ] + }, + "processing_system7_0_axi_periph_M03_AXI": { + "interface_ports": [ + "processing_system7_0_axi_periph/M03_AXI", + "dcsimpledrv_1/S00_AXI" + ] + }, + "processing_system7_0_M_AXI_GP0": { + "interface_ports": [ + "processing_system7_0/M_AXI_GP0", + "processing_system7_0_axi_periph/S00_AXI" + ] + }, + "processing_system7_0_axi_periph_M04_AXI": { + "interface_ports": [ + "processing_system7_0_axi_periph/M04_AXI", + "spi_leds_and_enc_0/S00_AXI" + ] + }, + "processing_system7_0_FIXED_IO": { + "interface_ports": [ + "FIXED_IO", + "processing_system7_0/FIXED_IO" + ] + }, + "audio_single_pwm_0_M00_AXI": { + "interface_ports": [ + "audio_single_pwm_0/M00_AXI", + "axi_mem_intercon/S01_AXI" + ] + }, + "display_16bit_cmd_data_bus_0_M00_AXI": { + "interface_ports": [ + "display_16bit_cmd_data_bus_0/M00_AXI", + "axi_mem_intercon/S02_AXI" + ] + }, + "processing_system7_0_axi_periph_M02_AXI": { + "interface_ports": [ + "processing_system7_0_axi_periph/M02_AXI", + "dcsimpledrv_0/S00_AXI" + ] + } + }, + "nets": { + "processing_system7_0_FCLK_CLK0": { + "ports": [ + "processing_system7_0/FCLK_CLK0", + "processing_system7_0/M_AXI_GP0_ACLK", + "rst_processing_system7_0_100M/slowest_sync_clk", + "axi_pwm_coprocessor_0/m00_axi_aclk", + "processing_system7_0/S_AXI_GP0_ACLK", + "axi_pwm_coprocessor_0/s00_axi_aclk", + "servo_led_ps2_0/s00_axi_aclk", + "spi_leds_and_enc_0/s00_axi_aclk", + "audio_single_pwm_0/s00_axi_aclk", + "audio_single_pwm_0/m00_axi_aclk", + "display_16bit_cmd_data_bus_0/s00_axi_aclk", + "display_16bit_cmd_data_bus_0/m00_axi_aclk", + "dcsimpledrv_0/s00_axi_aclk", + "dcsimpledrv_1/s00_axi_aclk", + "processing_system7_0_axi_periph/ACLK", + "processing_system7_0_axi_periph/S00_ACLK", + "processing_system7_0_axi_periph/M00_ACLK", + "processing_system7_0_axi_periph/M01_ACLK", + "processing_system7_0_axi_periph/M02_ACLK", + "processing_system7_0_axi_periph/M03_ACLK", + "axi_mem_intercon/S00_ACLK", + "axi_mem_intercon/ACLK", + "axi_mem_intercon/M00_ACLK", + "processing_system7_0_axi_periph/M04_ACLK", + "processing_system7_0_axi_periph/M05_ACLK", + "processing_system7_0_axi_periph/M06_ACLK", + "axi_mem_intercon/S01_ACLK", + "axi_mem_intercon/S02_ACLK" + ] + }, + "processing_system7_0_FCLK_RESET0_N": { + "ports": [ + "processing_system7_0/FCLK_RESET0_N", + "rst_processing_system7_0_100M/ext_reset_in" + ] + }, + "rst_processing_system7_0_100M_peripheral_aresetn": { + "ports": [ + "rst_processing_system7_0_100M/peripheral_aresetn", + "axi_pwm_coprocessor_0/m00_axi_aresetn", + "axi_pwm_coprocessor_0/s00_axi_aresetn", + "servo_led_ps2_0/s00_axi_aresetn", + "spi_leds_and_enc_0/s00_axi_aresetn", + "audio_single_pwm_0/s00_axi_aresetn", + "audio_single_pwm_0/m00_axi_aresetn", + "display_16bit_cmd_data_bus_0/s00_axi_aresetn", + "display_16bit_cmd_data_bus_0/m00_axi_aresetn", + "dcsimpledrv_0/s00_axi_aresetn", + "dcsimpledrv_1/s00_axi_aresetn", + "processing_system7_0_axi_periph/S00_ARESETN", + "processing_system7_0_axi_periph/M00_ARESETN", + "processing_system7_0_axi_periph/M01_ARESETN", + "processing_system7_0_axi_periph/M02_ARESETN", + "processing_system7_0_axi_periph/M03_ARESETN", + "axi_mem_intercon/S00_ARESETN", + "axi_mem_intercon/M00_ARESETN", + "processing_system7_0_axi_periph/M04_ARESETN", + "processing_system7_0_axi_periph/M05_ARESETN", + "processing_system7_0_axi_periph/M06_ARESETN", + "axi_mem_intercon/S01_ARESETN", + "axi_mem_intercon/S02_ARESETN" + ] + }, + "rst_processing_system7_0_100M_interconnect_aresetn": { + "ports": [ + "rst_processing_system7_0_100M/interconnect_aresetn", + "processing_system7_0_axi_periph/ARESETN", + "axi_mem_intercon/ARESETN" + ] + }, + "canbench_cc_gpio_0_GPIO_I": { + "ports": [ + "canbench_cc_gpio_0/GPIO_I", + "processing_system7_0/GPIO_I" + ] + }, + "processing_system7_0_GPIO_O": { + "ports": [ + "processing_system7_0/GPIO_O", + "canbench_cc_gpio_0/GPIO_O" + ] + }, + "xlconcat_0_dout": { + "ports": [ + "xlconcat_0/dout", + "processing_system7_0/IRQ_F2P" + ] + }, + "ENCDATA_1": { + "ports": [ + "ENCDATA", + "spi_leds_and_enc_0/spi_led_encin" + ] + }, + "spi_leds_and_enc_0_spi_led_reset": { + "ports": [ + "spi_leds_and_enc_0/spi_led_reset", + "RESET" + ] + }, + "spi_leds_and_enc_0_spi_led_clk": { + "ports": [ + "spi_leds_and_enc_0/spi_led_clk", + "LEDCLK" + ] + }, + "spi_leds_and_enc_0_spi_led_cs": { + "ports": [ + "spi_leds_and_enc_0/spi_led_cs", + "LEDCS" + ] + }, + "spi_leds_and_enc_0_spi_led_data": { + "ports": [ + "spi_leds_and_enc_0/spi_led_data", + "LEDDATA" + ] + }, + "servo_led_ps2_0_SERVO1": { + "ports": [ + "servo_led_ps2_0/SERVO1", + "SERVO1" + ] + }, + "servo_led_ps2_0_SERVO2": { + "ports": [ + "servo_led_ps2_0/SERVO2", + "SERVO2" + ] + }, + "servo_led_ps2_0_SERVO3": { + "ports": [ + "servo_led_ps2_0/SERVO3", + "SERVO3" + ] + }, + "Net": { + "ports": [ + "SERVO4", + "servo_led_ps2_0/SERVO4" + ] + }, + "audio_single_pwm_0_irq_rq_out": { + "ports": [ + "audio_single_pwm_0/irq_rq_out", + "xlconcat_0/In0" + ] + }, + "processing_system7_0_CAN0_PHY_TX": { + "ports": [ + "processing_system7_0/CAN0_PHY_TX", + "CAN1_TXD" + ] + }, + "processing_system7_0_CAN1_PHY_TX": { + "ports": [ + "processing_system7_0/CAN1_PHY_TX", + "CAN2_TXD" + ] + }, + "CAN1_RXD_1": { + "ports": [ + "CAN1_RXD", + "processing_system7_0/CAN0_PHY_RX" + ] + }, + "CAN2_RXD_1": { + "ports": [ + "CAN2_RXD", + "processing_system7_0/CAN1_PHY_RX" + ] + }, + "Net1": { + "ports": [ + "LCD_D", + "display_16bit_cmd_data_bus_0/lcd_data" + ] + }, + "display_16bit_cmd_data_bus_0_irq_rq_out": { + "ports": [ + "display_16bit_cmd_data_bus_0/irq_rq_out", + "xlconcat_0/In1" + ] + }, + "display_16bit_cmd_data_bus_0_lcd_res_n": { + "ports": [ + "display_16bit_cmd_data_bus_0/lcd_res_n", + "LCD_RST" + ] + }, + "display_16bit_cmd_data_bus_0_lcd_wr_n": { + "ports": [ + "display_16bit_cmd_data_bus_0/lcd_wr_n", + "LCD_WR" + ] + }, + "display_16bit_cmd_data_bus_0_lcd_dc": { + "ports": [ + "display_16bit_cmd_data_bus_0/lcd_dc", + "LCD_RS" + ] + }, + "audio_single_pwm_0_speaker_pwm_out": { + "ports": [ + "audio_single_pwm_0/speaker_pwm_out", + "SPEAKER" + ] + }, + "display_16bit_cmd_data_bus_0_lcd_cs_n": { + "ports": [ + "display_16bit_cmd_data_bus_0/lcd_cs_n", + "LCD_CS" + ] + }, + "dcsimpledrv_0_IRC_A_MON": { + "ports": [ + "dcsimpledrv_0/IRC_A_MON", + "xlconcat_1/In0" + ] + }, + "dcsimpledrv_0_IRC_B_MON": { + "ports": [ + "dcsimpledrv_0/IRC_B_MON", + "xlconcat_1/In1" + ] + }, + "dcsimpledrv_0_IRC_IRQ_MON": { + "ports": [ + "dcsimpledrv_0/IRC_IRQ_MON", + "xlconcat_1/In2" + ] + }, + "dcsimpledrv_0_IRC_CHG_MON": { + "ports": [ + "dcsimpledrv_0/IRC_CHG_MON", + "xlconcat_1/In3" + ] + }, + "dcsimpledrv_1_IRC_A_MON": { + "ports": [ + "dcsimpledrv_1/IRC_A_MON", + "xlconcat_1/In4" + ] + }, + "dcsimpledrv_1_IRC_B_MON": { + "ports": [ + "dcsimpledrv_1/IRC_B_MON", + "xlconcat_1/In5" + ] + }, + "dcsimpledrv_1_IRC_IRQ_MON": { + "ports": [ + "dcsimpledrv_1/IRC_IRQ_MON", + "xlconcat_1/In6" + ] + }, + "dcsimpledrv_1_IRC_CHG_MON": { + "ports": [ + "dcsimpledrv_1/IRC_CHG_MON", + "xlconcat_1/In7" + ] + }, + "xlconcat_1_dout": { + "ports": [ + "xlconcat_1/dout", + "canbench_cc_gpio_0/SW" + ] + }, + "dcsimpledrv_0_PWM_A": { + "ports": [ + "dcsimpledrv_0/PWM_A", + "PWM_A_0" + ] + }, + "dcsimpledrv_0_PWM_B": { + "ports": [ + "dcsimpledrv_0/PWM_B", + "PWM_B_0" + ] + }, + "IRC_IRQ_0_1": { + "ports": [ + "IRC_IRQ_0", + "dcsimpledrv_0/IRC_IRQ" + ] + }, + "IRC_B_0_1": { + "ports": [ + "IRC_B_0", + "dcsimpledrv_0/IRC_B" + ] + }, + "IRC_A_0_1": { + "ports": [ + "IRC_A_0", + "dcsimpledrv_0/IRC_A" + ] + }, + "IRC_A_1_1": { + "ports": [ + "IRC_A_1", + "dcsimpledrv_1/IRC_A" + ] + }, + "IRC_B_1_1": { + "ports": [ + "IRC_B_1", + "dcsimpledrv_1/IRC_B" + ] + }, + "IRC_IRQ_1_1": { + "ports": [ + "IRC_IRQ_1", + "dcsimpledrv_1/IRC_IRQ" + ] + }, + "dcsimpledrv_1_PWM_B": { + "ports": [ + "dcsimpledrv_1/PWM_B", + "PWM_B_1" + ] + }, + "dcsimpledrv_1_PWM_A": { + "ports": [ + "dcsimpledrv_1/PWM_A", + "PWM_A_1" + ] + } + }, + "addressing": { + "/processing_system7_0": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32", + "segments": { + "SEG_audio_single_pwm_0_S00_AXI_reg": { + "address_block": "/audio_single_pwm_0/S00_AXI/S00_AXI_reg", + "offset": "0x43C60000", + "range": "64K" + }, + "SEG_axi_pwm_coprocessor_0_S00_AXI_reg": { + "address_block": "/axi_pwm_coprocessor_0/S00_AXI/S00_AXI_reg", + "offset": "0x43C10000", + "range": "4K" + }, + "SEG_dcsimpledrv_0_S00_AXI_reg": { + "address_block": "/dcsimpledrv_0/S00_AXI/S00_AXI_reg", + "offset": "0x43C20000", + "range": "64K" + }, + "SEG_dcsimpledrv_1_S00_AXI_reg": { + "address_block": "/dcsimpledrv_1/S00_AXI/S00_AXI_reg", + "offset": "0x43C30000", + "range": "64K" + }, + "SEG_display_16bit_cmd_data_bus_0_S00_AXI_reg": { + "address_block": "/display_16bit_cmd_data_bus_0/S00_AXI/S00_AXI_reg", + "offset": "0x43C00000", + "range": "64K" + }, + "SEG_servo_led_ps2_0_S00_AXI_reg": { + "address_block": "/servo_led_ps2_0/S00_AXI/S00_AXI_reg", + "offset": "0x43C50000", + "range": "4K" + }, + "SEG_spi_leds_and_enc_0_S00_AXI_reg": { + "address_block": "/spi_leds_and_enc_0/S00_AXI/S00_AXI_reg", + "offset": "0x43C40000", + "range": "4K" + } + } + } + } + }, + "/axi_pwm_coprocessor_0": { + "address_spaces": { + "M00_AXI": { + "range": "4G", + "width": "32", + "segments": { + "SEG_processing_system7_0_GP0_DDR_LOWOCM": { + "address_block": "/processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM", + "offset": "0x00000000", + "range": "1G" + }, + "SEG_processing_system7_0_GP0_IOP": { + "address_block": "/processing_system7_0/S_AXI_GP0/GP0_IOP", + "offset": "0xE0000000", + "range": "4M" + }, + "SEG_processing_system7_0_GP0_M_AXI_GP0": { + "address_block": "/processing_system7_0/S_AXI_GP0/GP0_M_AXI_GP0", + "offset": "0x40000000", + "range": "1G" + }, + "SEG_processing_system7_0_GP0_QSPI_LINEAR": { + "address_block": "/processing_system7_0/S_AXI_GP0/GP0_QSPI_LINEAR", + "offset": "0xFC000000", + "range": "16M" + } + } + } + } + }, + "/audio_single_pwm_0": { + "address_spaces": { + "M00_AXI": { + "range": "4G", + "width": "32", + "segments": { + "SEG_processing_system7_0_GP0_DDR_LOWOCM": { + "address_block": "/processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM", + "offset": "0x00000000", + "range": "1G" + }, + "SEG_processing_system7_0_GP0_IOP": { + "address_block": "/processing_system7_0/S_AXI_GP0/GP0_IOP", + "offset": "0xE0000000", + "range": "4M" + }, + "SEG_processing_system7_0_GP0_M_AXI_GP0": { + "address_block": "/processing_system7_0/S_AXI_GP0/GP0_M_AXI_GP0", + "offset": "0x40000000", + "range": "1G" + }, + "SEG_processing_system7_0_GP0_QSPI_LINEAR": { + "address_block": "/processing_system7_0/S_AXI_GP0/GP0_QSPI_LINEAR", + "offset": "0xFC000000", + "range": "16M" + } + } + } + } + }, + "/display_16bit_cmd_data_bus_0": { + "address_spaces": { + "M00_AXI": { + "range": "4G", + "width": "32", + "segments": { + "SEG_processing_system7_0_GP0_DDR_LOWOCM": { + "address_block": "/processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM", + "offset": "0x00000000", + "range": "1G" + }, + "SEG_processing_system7_0_GP0_IOP": { + "address_block": "/processing_system7_0/S_AXI_GP0/GP0_IOP", + "offset": "0xE0000000", + "range": "4M" + }, + "SEG_processing_system7_0_GP0_M_AXI_GP0": { + "address_block": "/processing_system7_0/S_AXI_GP0/GP0_M_AXI_GP0", + "offset": "0x40000000", + "range": "1G" + }, + "SEG_processing_system7_0_GP0_QSPI_LINEAR": { + "address_block": "/processing_system7_0/S_AXI_GP0/GP0_QSPI_LINEAR", + "offset": "0xFC000000", + "range": "16M" + } + } + } + } + } + } + } +} \ No newline at end of file