From: Pavel Pisa Date: Tue, 24 Jan 2017 22:30:28 +0000 (+0100) Subject: microzed_apo: IP skeleton of SPI connected LEDs and encoders. X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/zynq/canbench-sw.git/commitdiff_plain/e54d4fde51db20b02797d512f906aae6a784fc10 microzed_apo: IP skeleton of SPI connected LEDs and encoders. Signed-off-by: Pavel Pisa --- diff --git a/system/ip/spi_leds_and_enc_1.0/bd/bd.tcl b/system/ip/spi_leds_and_enc_1.0/bd/bd.tcl new file mode 100644 index 0000000..4804aeb --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/system/ip/spi_leds_and_enc_1.0/component.xml b/system/ip/spi_leds_and_enc_1.0/component.xml new file mode 100644 index 0000000..47b7fcb --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/component.xml @@ -0,0 +1,853 @@ + + + user.org + user + spi_leds_and_enc + 1.0 + + + S00_AXI + + + + + + + + + AWADDR + + + s00_axi_awaddr + + + + + AWPROT + + + s00_axi_awprot + + + + + AWVALID + + + s00_axi_awvalid + + + + + AWREADY + + + s00_axi_awready + + + + + WDATA + + + s00_axi_wdata + + + + + WSTRB + + + s00_axi_wstrb + + + + + WVALID + + + s00_axi_wvalid + + + + + WREADY + + + s00_axi_wready + + + + + BRESP + + + s00_axi_bresp + + + + + BVALID + + + s00_axi_bvalid + + + + + BREADY + + + s00_axi_bready + + + + + ARADDR + + + s00_axi_araddr + + + + + ARPROT + + + s00_axi_arprot + + + + + ARVALID + + + s00_axi_arvalid + + + + + ARREADY + + + s00_axi_arready + + + + + RDATA + + + s00_axi_rdata + + + + + RRESP + + + s00_axi_rresp + + + + + RVALID + + + s00_axi_rvalid + + + + + RREADY + + + s00_axi_rready + + + + + + WIZ_DATA_WIDTH + 32 + + + WIZ_NUM_REG + 16 + + + SUPPORTS_NARROW_BURST + 0 + + + + + S00_AXI_RST + + + + + + + RST + + + s00_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + S00_AXI_CLK + + + + + + + CLK + + + s00_axi_aclk + + + + + + ASSOCIATED_BUSIF + S00_AXI + + + ASSOCIATED_RESET + s00_axi_aresetn + + + + + + + S00_AXI + + S00_AXI_reg + 0 + 4096 + 32 + register + + + OFFSET_BASE_PARAM + C_S00_AXI_BASEADDR + + + OFFSET_HIGH_PARAM + C_S00_AXI_HIGHADDR + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + spi_leds_and_enc_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + spi_leds_and_enc_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + xilinx_softwaredriver + Software Driver + :vivado.xilinx.com:sw.driver + + xilinx_softwaredriver_view_fileset + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + + + spi_led_reset + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + spi_led_clk + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + spi_led_cs + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + spi_led_data + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + spi_led_encin + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_bvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_bready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_arvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_arready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_rvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_rready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_aclk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_aresetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_S00_AXI_DATA_WIDTH + C S00 AXI DATA WIDTH + Width of S_AXI data bus + 32 + + + C_S00_AXI_ADDR_WIDTH + C S00 AXI ADDR WIDTH + Width of S_AXI address bus + 6 + + + + + + choice_list_6fc15197 + 32 + + + choice_pairs_ce1226b1 + 1 + 0 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/spi_leds_and_enc_v1_0_S00_AXI.vhd + vhdlSource + + + hdl/spi_leds_and_enc_v1_0.vhd + vhdlSource + CHECKSUM_df5775b0 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/spi_leds_and_enc_v1_0_S00_AXI.vhd + vhdlSource + + + hdl/spi_leds_and_enc_v1_0.vhd + vhdlSource + + + + xilinx_softwaredriver_view_fileset + + drivers/spi_leds_and_enc_v1_0/data/spi_leds_and_enc.mdd + mdd + driver_mdd + + + drivers/spi_leds_and_enc_v1_0/data/spi_leds_and_enc.tcl + tclSource + driver_tcl + + + drivers/spi_leds_and_enc_v1_0/src/Makefile + driver_src + + + drivers/spi_leds_and_enc_v1_0/src/spi_leds_and_enc.h + cSource + driver_src + + + drivers/spi_leds_and_enc_v1_0/src/spi_leds_and_enc.c + cSource + driver_src + + + drivers/spi_leds_and_enc_v1_0/src/spi_leds_and_enc_selftest.c + cSource + driver_src + + + + xilinx_xpgui_view_fileset + + xgui/spi_leds_and_enc_v1_0.tcl + tclSource + CHECKSUM_fd592ead + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + SPI connected LEDs and encoders + + + C_S00_AXI_DATA_WIDTH + C S00 AXI DATA WIDTH + Width of S_AXI data bus + 32 + + + + false + + + + + + C_S00_AXI_ADDR_WIDTH + C S00 AXI ADDR WIDTH + Width of S_AXI address bus + 6 + + + + false + + + + + + C_S00_AXI_BASEADDR + C S00 AXI BASEADDR + 0xFFFFFFFF + + + + false + + + + + + C_S00_AXI_HIGHADDR + C S00 AXI HIGHADDR + 0x00000000 + + + + false + + + + + + Component_Name + spi_leds_and_enc_v1_0 + + + + + + zynq + + + AXI_Peripheral + + spi_leds_and_enc_v1.0 + 1 + 2017-01-23T01:27:21Z + + /home/pi/fpga/zynq/canbech-sw/system/ip_repo/spi_leds_and_enc_1.0 + + + + 2016.1 + + + diff --git a/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/data/spi_leds_and_enc.mdd b/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/data/spi_leds_and_enc.mdd new file mode 100644 index 0000000..4a6934f --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/data/spi_leds_and_enc.mdd @@ -0,0 +1,10 @@ + + +OPTION psf_version = 2.1; + +BEGIN DRIVER spi_leds_and_enc + OPTION supported_peripherals = (spi_leds_and_enc); + OPTION copyfiles = all; + OPTION VERSION = 1.0; + OPTION NAME = spi_leds_and_enc; +END DRIVER diff --git a/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/data/spi_leds_and_enc.tcl b/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/data/spi_leds_and_enc.tcl new file mode 100644 index 0000000..9313dcf --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/data/spi_leds_and_enc.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "spi_leds_and_enc" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" +} diff --git a/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/src/Makefile b/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/src/Makefile new file mode 100644 index 0000000..10945a7 --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/src/Makefile @@ -0,0 +1,26 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + +libs: + echo "Compiling spi_leds_and_enc..." + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/src/spi_leds_and_enc.c b/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/src/spi_leds_and_enc.c new file mode 100644 index 0000000..05ad4e0 --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/src/spi_leds_and_enc.c @@ -0,0 +1,6 @@ + + +/***************************** Include Files *******************************/ +#include "spi_leds_and_enc.h" + +/************************** Function Definitions ***************************/ diff --git a/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/src/spi_leds_and_enc.h b/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/src/spi_leds_and_enc.h new file mode 100644 index 0000000..7c367ca --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/src/spi_leds_and_enc.h @@ -0,0 +1,91 @@ + +#ifndef SPI_LEDS_AND_ENC_H +#define SPI_LEDS_AND_ENC_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG0_OFFSET 0 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG1_OFFSET 4 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG2_OFFSET 8 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG3_OFFSET 12 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG4_OFFSET 16 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG5_OFFSET 20 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG6_OFFSET 24 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG7_OFFSET 28 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG8_OFFSET 32 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG9_OFFSET 36 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG10_OFFSET 40 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG11_OFFSET 44 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG12_OFFSET 48 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG13_OFFSET 52 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG14_OFFSET 56 +#define SPI_LEDS_AND_ENC_S00_AXI_SLV_REG15_OFFSET 60 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a SPI_LEDS_AND_ENC register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the SPI_LEDS_AND_ENCdevice. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void SPI_LEDS_AND_ENC_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define SPI_LEDS_AND_ENC_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a SPI_LEDS_AND_ENC register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the SPI_LEDS_AND_ENC device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 SPI_LEDS_AND_ENC_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define SPI_LEDS_AND_ENC_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the SPI_LEDS_AND_ENC instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus SPI_LEDS_AND_ENC_Reg_SelfTest(void * baseaddr_p); + +#endif // SPI_LEDS_AND_ENC_H diff --git a/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/src/spi_leds_and_enc_selftest.c b/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/src/spi_leds_and_enc_selftest.c new file mode 100644 index 0000000..472ea47 --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/drivers/spi_leds_and_enc_v1_0/src/spi_leds_and_enc_selftest.c @@ -0,0 +1,60 @@ + +/***************************** Include Files *******************************/ +#include "spi_leds_and_enc.h" +#include "xparameters.h" +#include "stdio.h" +#include "xil_io.h" + +/************************** Constant Definitions ***************************/ +#define READ_WRITE_MUL_FACTOR 0x10 + +/************************** Function Definitions ***************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the SPI_LEDS_AND_ENCinstance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus SPI_LEDS_AND_ENC_Reg_SelfTest(void * baseaddr_p) +{ + u32 baseaddr; + int write_loop_index; + int read_loop_index; + int Index; + + baseaddr = (u32) baseaddr_p; + + xil_printf("******************************\n\r"); + xil_printf("* User Peripheral Self Test\n\r"); + xil_printf("******************************\n\n\r"); + + /* + * Write to user logic slave module register(s) and read back + */ + xil_printf("User logic slave module test...\n\r"); + + for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) + SPI_LEDS_AND_ENC_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); + for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) + if ( SPI_LEDS_AND_ENC_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ + xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); + return XST_FAILURE; + } + + xil_printf(" - slave register write/read passed\n\n\r"); + + return XST_SUCCESS; +} diff --git a/system/ip/spi_leds_and_enc_1.0/example_designs/bfm_design/design.tcl b/system/ip/spi_leds_and_enc_1.0/example_designs/bfm_design/design.tcl new file mode 100644 index 0000000..a41b7ad --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/example_designs/bfm_design/design.tcl @@ -0,0 +1,91 @@ +proc create_ipi_design { offsetfile design_name } { + create_bd_design $design_name + open_bd_design $design_name + + # Create Clock and Reset Ports + set ACLK [ create_bd_port -dir I -type clk ACLK ] + set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK + set ARESETN [ create_bd_port -dir I -type rst ARESETN ] + set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN + set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK + + # Create instance: spi_leds_and_enc_0, and set properties + set spi_leds_and_enc_0 [ create_bd_cell -type ip -vlnv user.org:user:spi_leds_and_enc:1.0 spi_leds_and_enc_0] + + # Create instance: master_0, and set properties + set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm master_0] + set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} ] $master_0 + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI_LITE] [get_bd_intf_pins spi_leds_and_enc_0/S00_AXI] + + # Create port connections + connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/M_AXI_LITE_ACLK] [get_bd_pins spi_leds_and_enc_0/S00_AXI_ACLK] + connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/M_AXI_LITE_ARESETN] [get_bd_pins spi_leds_and_enc_0/S00_AXI_ARESETN] + + # Auto assign address + assign_bd_address + + # Copy all address to interface_address.vh file + set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]] + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/spi_leds_and_enc_v1_0_tb_include.vh" + set fp [open $offset_file "w"] + puts $fp "`ifndef spi_leds_and_enc_v1_0_tb_include_vh_" + puts $fp "`define spi_leds_and_enc_v1_0_tb_include_vh_\n" + puts $fp "//Configuration current bd names" + puts $fp "`define BD_INST_NAME ${design_name}_i" + puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n" + puts $fp "//Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs -of_objects [get_bd_addr_spaces master_0/Data_lite]]] + set offset_hex [string replace $offset 0 1 "32'h"] + puts $fp "`define S00_AXI_SLAVE_ADDRESS ${offset_hex}" + + puts $fp "`endif" + close $fp +} + +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:spi_leds_and_enc:1.0]]]] +set test_bench_file ${ip_path}/example_designs/bfm_design/spi_leds_and_enc_v1_0_tb.v +set interface_address_vh_file "" + +# Set IP Repository and Update IP Catalogue +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "spi_leds_and_enc_v1_0_bfm_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +create_ipi_design interface_address_vh_file ${design_name} +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +set_property SOURCE_SET sources_1 [get_filesets sim_1] +import_files -fileset sim_1 -norecurse -force $test_bench_file +remove_files -quiet -fileset sim_1 spi_leds_and_enc_v1_0_tb_include.vh +import_files -fileset sim_1 -norecurse -force $interface_address_vh_file +set_property top spi_leds_and_enc_v1_0_tb [get_filesets sim_1] +set_property top_lib {} [get_filesets sim_1] +set_property top_file {} [get_filesets sim_1] +launch_xsim -simset sim_1 -mode behavioral +restart +run 1000 us diff --git a/system/ip/spi_leds_and_enc_1.0/example_designs/bfm_design/spi_leds_and_enc_v1_0_tb.v b/system/ip/spi_leds_and_enc_1.0/example_designs/bfm_design/spi_leds_and_enc_v1_0_tb.v new file mode 100644 index 0000000..8e6e26d --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/example_designs/bfm_design/spi_leds_and_enc_v1_0_tb.v @@ -0,0 +1,185 @@ + +`timescale 1 ns / 1 ps + +`include "spi_leds_and_enc_v1_0_tb_include.vh" + +// lite_response Type Defines +`define RESPONSE_OKAY 2'b00 +`define RESPONSE_EXOKAY 2'b01 +`define RESP_BUS_WIDTH 2 +`define BURST_TYPE_INCR 2'b01 +`define BURST_TYPE_WRAP 2'b10 + +// AMBA AXI4 Lite Range Constants +`define S00_AXI_MAX_BURST_LENGTH 1 +`define S00_AXI_DATA_BUS_WIDTH 32 +`define S00_AXI_ADDRESS_BUS_WIDTH 32 +`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8 + +module spi_leds_and_enc_v1_0_tb; + reg tb_ACLK; + reg tb_ARESETn; + + // Create an instance of the example tb + `BD_WRAPPER dut (.ACLK(tb_ACLK), + .ARESETN(tb_ARESETn)); + + // Local Variables + + // AMBA S00_AXI AXI4 Lite Local Reg + reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite; + reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0]; + reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response; + reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress; + reg [3-1:0] S00_AXI_mtestProtection_lite; + integer S00_AXI_mtestvectorlite; // Master side testvector + integer S00_AXI_mtestdatasizelite; + integer result_slave_lite; + + + // Simple Reset Generator and test + initial begin + tb_ARESETn = 1'b0; + #500; + // Release the reset on the posedge of the clk. + @(posedge tb_ACLK); + tb_ARESETn = 1'b1; + @(posedge tb_ACLK); + end + + // Simple Clock Generator + initial tb_ACLK = 1'b0; + always #10 tb_ACLK = !tb_ACLK; + + //------------------------------------------------------------------------ + // TEST LEVEL API: CHECK_RESPONSE_OKAY + //------------------------------------------------------------------------ + // Description: + // CHECK_RESPONSE_OKAY(lite_response) + // This task checks if the return lite_response is equal to OKAY + //------------------------------------------------------------------------ + task automatic CHECK_RESPONSE_OKAY; + input [`RESP_BUS_WIDTH-1:0] response; + begin + if (response !== `RESPONSE_OKAY) begin + $display("TESTBENCH ERROR! lite_response is not OKAY", + "\n expected = 0x%h",`RESPONSE_OKAY, + "\n actual = 0x%h",response); + $stop; + end + end + endtask + + //------------------------------------------------------------------------ + // TEST LEVEL API: COMPARE_LITE_DATA + //------------------------------------------------------------------------ + // Description: + // COMPARE_LITE_DATA(expected,actual) + // This task checks if the actual data is equal to the expected data. + // X is used as don't care but it is not permitted for the full vector + // to be don't care. + //------------------------------------------------------------------------ + `define S_AXI_DATA_BUS_WIDTH 32 + task automatic COMPARE_LITE_DATA; + input [`S_AXI_DATA_BUS_WIDTH-1:0]expected; + input [`S_AXI_DATA_BUS_WIDTH-1:0]actual; + begin + if (expected === 'hx || actual === 'hx) begin + $display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); + result_slave_lite = 0; + $stop; + end + + if (actual != expected) begin + $display("TESTBENCH ERROR! Data expected is not equal to actual.", + "\nexpected = 0x%h",expected, + "\nactual = 0x%h",actual); + result_slave_lite = 0; + $stop; + end + else + begin + $display("TESTBENCH Passed! Data expected is equal to actual.", + "\n expected = 0x%h",expected, + "\n actual = 0x%h",actual); + end + end + endtask + + task automatic S00_AXI_TEST; + begin + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST : S00_AXI"); + $display("Simple register write and read example"); + $display("---------------------------------------------------------"); + + S00_AXI_mtestvectorlite = 0; + S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS; + S00_AXI_mtestProtection_lite = 0; + S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE; + + result_slave_lite = 1; + + for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1) + begin + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress, + S00_AXI_mtestProtection_lite, + S00_AXI_test_data_lite[S00_AXI_mtestvectorlite], + S00_AXI_mtestdatasizelite, + S00_AXI_lite_response); + $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response); + CHECK_RESPONSE_OKAY(S00_AXI_lite_response); + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress, + S00_AXI_mtestProtection_lite, + S00_AXI_rd_data_lite, + S00_AXI_lite_response); + $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response); + CHECK_RESPONSE_OKAY(S00_AXI_lite_response); + COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite); + $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite); + S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004; + end + + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); + if ( result_slave_lite ) begin + $display("PTGEN_TEST: PASSED!"); + end else begin + $display("PTGEN_TEST: FAILED!"); + end + $display("---------------------------------------------------------"); + end + endtask + + // Create the test vectors + initial begin + // When performing debug enable all levels of INFO messages. + wait(tb_ARESETn === 0) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1); + + // Create test data vectors + S00_AXI_test_data_lite[0] = 32'h0101FFFF; + S00_AXI_test_data_lite[1] = 32'habcd0001; + S00_AXI_test_data_lite[2] = 32'hdead0011; + S00_AXI_test_data_lite[3] = 32'hbeef0011; + end + + // Drive the BFM + initial begin + // Wait for end of reset + wait(tb_ARESETn === 0) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + + S00_AXI_TEST(); + + end + +endmodule diff --git a/system/ip/spi_leds_and_enc_1.0/example_designs/debug_hw_design/design.tcl b/system/ip/spi_leds_and_enc_1.0/example_designs/debug_hw_design/design.tcl new file mode 100644 index 0000000..d8a024f --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/example_designs/debug_hw_design/design.tcl @@ -0,0 +1,175 @@ + +proc create_ipi_design { offsetfile design_name } { + + create_bd_design $design_name + open_bd_design $design_name + + # Create and configure Clock/Reset + create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0 + create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0 + + #check if current_board is set, if true - figure out required clocks. + set is_board_clock_found 0 + set is_board_reset_found 0 + set external_reset_port "" + set external_clock_port "" + + if { [current_board_part -quiet] != "" } { + + #check if any reset interface exists in board. + set board_reset [lindex [get_board_part_interfaces -filter { BUSDEF_NAME == reset_rtl && MODE == slave }] 0 ] + if { $board_reset ne "" } { + set is_board_reset_found 1 + apply_board_connection -board_interface $board_reset -ip_intf sys_clk_0/reset -diagram [current_bd_design] + apply_board_connection -board_interface $board_reset -ip_intf sys_reset_0/ext_reset -diagram [current_bd_design] + set external_rst [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/reset]]] + if { $external_rst ne "" } { + set external_reset_port [get_property NAME $external_rst] + } + } else { + send_msg "ptgen 51-200" WARNING "No reset interface found in current_board, Users may need to specify the location constraints manually." + } + + # check for differential clock, exclude any special clocks which has TYPE property. + set board_clock_busifs "" + foreach busif [get_board_part_interfaces -filter "BUSDEF_NAME == diff_clock_rtl"] { + set type [get_property PARAM.TYPE $busif] + if { $type == "" } { + set board_clock_busifs $busif + break + } + } + if { $board_clock_busifs ne "" } { + apply_board_connection -board_interface $board_clock_busifs -ip_intf sys_clk_0/CLK_IN1_D -diagram [current_bd_design] + set is_board_clock_found 1 + } else { + # check for single ended clock + set board_sclock_busifs [lindex [get_board_part_interfaces -filter "BUSDEF_NAME == clock_rtl"] 0 ] + if { $board_sclock_busifs ne "" } { + apply_board_connection -board_interface $board_sclock_busifs -ip_intf sys_clk_0/clock_CLK_IN1 -diagram [current_bd_design] + set external_clk [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/clk_in1]]] + if { $external_clk ne "" } { + set external_clock_port [get_property NAME $external_clk] + } + set is_board_clock_found 1 + } else { + send_msg "ptgen 51-200" WARNING "No clock interface found in current_board, Users may need to specify the location constraints manually." + } + } + + } else { + send_msg "ptgen 51-201" WARNING "No board selected in current_project. Users may need to specify the location constraints manually." + } + + #if there is no corresponding board interface found, assume constraints will be provided manually while pin planning. + if { $is_board_reset_found == 0 } { + create_bd_port -dir I -type rst reset_rtl + set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset] + set external_reset_port reset_rtl + } + if { $is_board_clock_found == 0 } { + create_bd_port -dir I -type clk clock_rtl + connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl] + set external_clock_port clock_rtl + } + + #Avoid IPI DRC, make clock port synchronous to reset + if { $external_clock_port ne "" && $external_reset_port ne "" } { + set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port] + } + + # Connect other sys_reset pins + connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked] + + # Create instance: spi_leds_and_enc_0, and set properties + set spi_leds_and_enc_0 [ create_bd_cell -type ip -vlnv user.org:user:spi_leds_and_enc:1.0 spi_leds_and_enc_0 ] + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ] + set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0] + connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Create instance: axi_peri_interconnect, and set properties + set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ] + connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn] + set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI] + + set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Connect all clock & reset of spi_leds_and_enc_0 slave interfaces.. + connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins spi_leds_and_enc_0/S00_AXI] + connect_bd_net [get_bd_pins spi_leds_and_enc_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins spi_leds_and_enc_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + + # Auto assign address + assign_bd_address + + # Copy all address to spi_leds_and_enc_v1_0_include.tcl file + set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/spi_leds_and_enc_v1_0_include.tcl" + set fp [open $offset_file "w"] + puts $fp "# Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_spi_leds_and_enc_0_S00_AXI_* ]] + puts $fp "set s00_axi_addr ${offset}" + + close $fp +} + +# Set IP Repository and Update IP Catalogue +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:spi_leds_and_enc:1.0]]]] +set hw_test_file ${ip_path}/example_designs/debug_hw_design/spi_leds_and_enc_v1_0_hw_test.tcl + +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "spi_leds_and_enc_v1_0_hw_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +set intf_address_include_file "" +create_ipi_design intf_address_include_file ${design_name} +save_bd_design +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +puts "-------------------------------------------------------------------------------------------------" +puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, " +puts " please perform following steps to test design in targeted board." +puts "1. Generate bitstream" +puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target" +puts "3. Download generated bitstream" +puts "4. Run generated hardware test using below command, this invokes basic read/write operation" +puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0" +puts " : source -notrace ${hw_test_file}" +puts "-------------------------------------------------------------------------------------------------" + diff --git a/system/ip/spi_leds_and_enc_1.0/example_designs/debug_hw_design/spi_leds_and_enc_v1_0_hw_test.tcl b/system/ip/spi_leds_and_enc_1.0/example_designs/debug_hw_design/spi_leds_and_enc_v1_0_hw_test.tcl new file mode 100644 index 0000000..d70306b --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/example_designs/debug_hw_design/spi_leds_and_enc_v1_0_hw_test.tcl @@ -0,0 +1,45 @@ +# Runtime Tcl commands to interact with - spi_leds_and_enc_v1_0 + +# Sourcing design address info tcl +set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd +source ${bd_path}/spi_leds_and_enc_v1_0_include.tcl + +# jtag axi master interface hardware name, change as per your design. +set jtag_axi_master hw_axi_1 +set ec 0 + +# hw test script +# Delete all previous axis transactions +if { [llength [get_hw_axi_txns -quiet]] } { + delete_hw_axi_txn [get_hw_axi_txns -quiet] +} + + +# Test all lite slaves. +set wdata_1 abcd1234 + +# Test: S00_AXI +# Create a write transaction at s00_axi_addr address +create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1 +# Create a read transaction at s00_axi_addr address +create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr +# Initiate transactions +run_hw_axi r_s00_axi_addr +run_hw_axi w_s00_axi_addr +run_hw_axi r_s00_axi_addr +set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]] +# Compare read data +if { $rdata_tmp == $wdata_1 } { + puts "Data comparison test pass for - S00_AXI" +} else { + puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp" + inc ec +} + +# Check error flag +if { $ec == 0 } { + puts "PTGEN_TEST: PASSED!" +} else { + puts "PTGEN_TEST: FAILED!" +} + diff --git a/system/ip/spi_leds_and_enc_1.0/hdl/spi_leds_and_enc_v1_0.vhd b/system/ip/spi_leds_and_enc_1.0/hdl/spi_leds_and_enc_v1_0.vhd new file mode 100644 index 0000000..0cdc32f --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/hdl/spi_leds_and_enc_v1_0.vhd @@ -0,0 +1,122 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity spi_leds_and_enc_v1_0 is + generic ( + -- Users to add parameters here + + -- User parameters ends + -- Do not modify the parameters beyond this line + + + -- Parameters of Axi Slave Bus Interface S00_AXI + C_S00_AXI_DATA_WIDTH : integer := 32; + C_S00_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + -- Users to add ports here + spi_led_reset : out std_logic; + spi_led_clk : out std_logic; + spi_led_cs : out std_logic; + spi_led_data : out std_logic; + spi_led_encin : in std_logic; + -- User ports ends + -- Do not modify the ports beyond this line + + + -- Ports of Axi Slave Bus Interface S00_AXI + s00_axi_aclk : in std_logic; + s00_axi_aresetn : in std_logic; + s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_awprot : in std_logic_vector(2 downto 0); + s00_axi_awvalid : in std_logic; + s00_axi_awready : out std_logic; + s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); + s00_axi_wvalid : in std_logic; + s00_axi_wready : out std_logic; + s00_axi_bresp : out std_logic_vector(1 downto 0); + s00_axi_bvalid : out std_logic; + s00_axi_bready : in std_logic; + s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_arprot : in std_logic_vector(2 downto 0); + s00_axi_arvalid : in std_logic; + s00_axi_arready : out std_logic; + s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_rresp : out std_logic_vector(1 downto 0); + s00_axi_rvalid : out std_logic; + s00_axi_rready : in std_logic + ); +end spi_leds_and_enc_v1_0; + +architecture arch_imp of spi_leds_and_enc_v1_0 is + + -- component declaration + component spi_leds_and_enc_v1_0_S00_AXI is + generic ( + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic + ); + end component spi_leds_and_enc_v1_0_S00_AXI; + +begin + +-- Instantiation of Axi Bus Interface S00_AXI +spi_leds_and_enc_v1_0_S00_AXI_inst : spi_leds_and_enc_v1_0_S00_AXI + generic map ( + C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH + ) + port map ( + S_AXI_ACLK => s00_axi_aclk, + S_AXI_ARESETN => s00_axi_aresetn, + S_AXI_AWADDR => s00_axi_awaddr, + S_AXI_AWPROT => s00_axi_awprot, + S_AXI_AWVALID => s00_axi_awvalid, + S_AXI_AWREADY => s00_axi_awready, + S_AXI_WDATA => s00_axi_wdata, + S_AXI_WSTRB => s00_axi_wstrb, + S_AXI_WVALID => s00_axi_wvalid, + S_AXI_WREADY => s00_axi_wready, + S_AXI_BRESP => s00_axi_bresp, + S_AXI_BVALID => s00_axi_bvalid, + S_AXI_BREADY => s00_axi_bready, + S_AXI_ARADDR => s00_axi_araddr, + S_AXI_ARPROT => s00_axi_arprot, + S_AXI_ARVALID => s00_axi_arvalid, + S_AXI_ARREADY => s00_axi_arready, + S_AXI_RDATA => s00_axi_rdata, + S_AXI_RRESP => s00_axi_rresp, + S_AXI_RVALID => s00_axi_rvalid, + S_AXI_RREADY => s00_axi_rready + ); + + -- Add user logic here + + -- User logic ends + +end arch_imp; diff --git a/system/ip/spi_leds_and_enc_1.0/hdl/spi_leds_and_enc_v1_0_S00_AXI.vhd b/system/ip/spi_leds_and_enc_1.0/hdl/spi_leds_and_enc_v1_0_S00_AXI.vhd new file mode 100644 index 0000000..6a55a35 --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/hdl/spi_leds_and_enc_v1_0_S00_AXI.vhd @@ -0,0 +1,541 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity spi_leds_and_enc_v1_0_S00_AXI is + generic ( + -- Users to add parameters here + + -- User parameters ends + -- Do not modify the parameters beyond this line + + -- Width of S_AXI data bus + C_S_AXI_DATA_WIDTH : integer := 32; + -- Width of S_AXI address bus + C_S_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + -- Users to add ports here + + -- User ports ends + -- Do not modify the ports beyond this line + + -- Global Clock Signal + S_AXI_ACLK : in std_logic; + -- Global Reset Signal. This Signal is Active LOW + S_AXI_ARESETN : in std_logic; + -- Write address (issued by master, acceped by Slave) + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Write channel Protection type. This signal indicates the + -- privilege and security level of the transaction, and whether + -- the transaction is a data access or an instruction access. + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + -- Write address valid. This signal indicates that the master signaling + -- valid write address and control information. + S_AXI_AWVALID : in std_logic; + -- Write address ready. This signal indicates that the slave is ready + -- to accept an address and associated control signals. + S_AXI_AWREADY : out std_logic; + -- Write data (issued by master, acceped by Slave) + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Write strobes. This signal indicates which byte lanes hold + -- valid data. There is one write strobe bit for each eight + -- bits of the write data bus. + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + -- Write valid. This signal indicates that valid write + -- data and strobes are available. + S_AXI_WVALID : in std_logic; + -- Write ready. This signal indicates that the slave + -- can accept the write data. + S_AXI_WREADY : out std_logic; + -- Write response. This signal indicates the status + -- of the write transaction. + S_AXI_BRESP : out std_logic_vector(1 downto 0); + -- Write response valid. This signal indicates that the channel + -- is signaling a valid write response. + S_AXI_BVALID : out std_logic; + -- Response ready. This signal indicates that the master + -- can accept a write response. + S_AXI_BREADY : in std_logic; + -- Read address (issued by master, acceped by Slave) + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Protection type. This signal indicates the privilege + -- and security level of the transaction, and whether the + -- transaction is a data access or an instruction access. + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + -- Read address valid. This signal indicates that the channel + -- is signaling valid read address and control information. + S_AXI_ARVALID : in std_logic; + -- Read address ready. This signal indicates that the slave is + -- ready to accept an address and associated control signals. + S_AXI_ARREADY : out std_logic; + -- Read data (issued by slave) + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Read response. This signal indicates the status of the + -- read transfer. + S_AXI_RRESP : out std_logic_vector(1 downto 0); + -- Read valid. This signal indicates that the channel is + -- signaling the required read data. + S_AXI_RVALID : out std_logic; + -- Read ready. This signal indicates that the master can + -- accept the read data and response information. + S_AXI_RREADY : in std_logic + ); +end spi_leds_and_enc_v1_0_S00_AXI; + +architecture arch_imp of spi_leds_and_enc_v1_0_S00_AXI is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal byte_index : integer; + +begin + -- I/O Connections assignments + + S_AXI_AWREADY <= axi_awready; + S_AXI_WREADY <= axi_wready; + S_AXI_BRESP <= axi_bresp; + S_AXI_BVALID <= axi_bvalid; + S_AXI_ARREADY <= axi_arready; + S_AXI_RDATA <= axi_rdata; + S_AXI_RRESP <= axi_rresp; + S_AXI_RVALID <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awready <= '0'; + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then + -- Write Address latching + axi_awaddr <= S_AXI_AWADDR; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; + + process (S_AXI_ACLK) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and S_AXI_ARVALID = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= S_AXI_ARADDR; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, S_AXI_ARESETN, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + + -- Add user logic here + + -- User logic ends + +end arch_imp; diff --git a/system/ip/spi_leds_and_enc_1.0/xgui/spi_leds_and_enc_v1_0.tcl b/system/ip/spi_leds_and_enc_1.0/xgui/spi_leds_and_enc_v1_0.tcl new file mode 100644 index 0000000..d8bf174 --- /dev/null +++ b/system/ip/spi_leds_and_enc_1.0/xgui/spi_leds_and_enc_v1_0.tcl @@ -0,0 +1,62 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox] + set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH} + set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}] + set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH} + ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to validate C_S00_AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to validate C_S00_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { + # Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { + # Procedure called to validate C_S00_AXI_BASEADDR + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { + # Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { + # Procedure called to validate C_S00_AXI_HIGHADDR + return true +} + + +proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} +} +