From: Martin Jerabek Date: Thu, 12 May 2016 23:53:44 +0000 (+0200) Subject: sja1000: IP fixes, corrected device-tree entry, it works now X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/zynq/canbench-sw.git/commitdiff_plain/a9f1e455e73421dfede13efd167511860657f1d0 sja1000: IP fixes, corrected device-tree entry, it works now --- diff --git a/petalinux/subsystems/linux/configs/device-tree/system-top.dts b/petalinux/subsystems/linux/configs/device-tree/system-top.dts index b8ee1ca..d5ab8ba 100644 --- a/petalinux/subsystems/linux/configs/device-tree/system-top.dts +++ b/petalinux/subsystems/linux/configs/device-tree/system-top.dts @@ -7,6 +7,14 @@ compatible = "nxp,sja1000"; nxp,external-clock-frequency = <100000000>; interrupt-parent = <&intc>; - interrupts = <0 61 4>; + interrupts = <0 29 4>; + reg-io-width = <4>; +}; + +&sja1000_1 { + compatible = "nxp,sja1000"; + nxp,external-clock-frequency = <100000000>; + interrupt-parent = <&intc>; + interrupts = <0 30 4>; reg-io-width = <4>; }; diff --git a/system/ip/can_merge/can_merge.vhd b/system/ip/can_merge/can_merge.vhd index d7f580e..d68260b 100644 --- a/system/ip/can_merge/can_merge.vhd +++ b/system/ip/can_merge/can_merge.vhd @@ -14,10 +14,11 @@ entity can_merge is Port ( can_rx : out STD_LOGIC; can_tx1 : in STD_LOGIC := '1'; can_tx2 : in STD_LOGIC := '1'; - can_tx3 : in STD_LOGIC := '1'); + can_tx3 : in STD_LOGIC := '1'; + can_tx4 : in STD_LOGIC := '1'); end can_merge; architecture Behavioral of can_merge is begin - can_rx <= can_tx1 and can_tx2 and can_tx3; + can_rx <= can_tx1 and can_tx2 and can_tx3 and can_tx4; end Behavioral; diff --git a/system/ip/can_merge/component.xml b/system/ip/can_merge/component.xml index 44b9023..9f9afd6 100644 --- a/system/ip/can_merge/component.xml +++ b/system/ip/can_merge/component.xml @@ -18,7 +18,7 @@ viewChecksum - 5039bc21 + 96f5f6ad @@ -34,7 +34,7 @@ viewChecksum - 5039bc21 + 96f5f6ad @@ -115,6 +115,22 @@ + + can_tx4 + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + @@ -123,7 +139,7 @@ can_merge.vhd vhdlSource - CHECKSUM_5039bc21 + CHECKSUM_96f5f6ad @@ -160,17 +176,17 @@ /UserIP can_merge_v1_0 - 2 - 2016-03-24T16:51:44Z + 3 + 2016-05-12T21:21:05Z /home/martin/projects/cvut/bakalarka/canbench-sw/system/ip/can_merge - 2015.4 - - + 2016.1 + + diff --git a/system/ip/sja1000_1.0/component.xml b/system/ip/sja1000_1.0/component.xml index d9ea2a2..e1f6e50 100644 --- a/system/ip/sja1000_1.0/component.xml +++ b/system/ip/sja1000_1.0/component.xml @@ -307,7 +307,7 @@ viewChecksum - 586400b8 + a4eeabb5 @@ -322,7 +322,7 @@ viewChecksum - 586400b8 + a4eeabb5 @@ -385,7 +385,7 @@ in - 7 + 9 0 @@ -548,7 +548,7 @@ in - 7 + 9 0 @@ -714,7 +714,7 @@ C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus - 8 + 10 @@ -969,7 +969,7 @@ C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus - 8 + 10 @@ -1002,8 +1002,8 @@ AXI_Peripheral sja1000_v1.0 - 8 - 2016-05-11T17:43:43Z + 23 + 2016-05-12T18:22:23Z /home/martin/projects/cvut/bakalarka/canbench-sw/system/ip/sja1000_1.0 @@ -1012,10 +1012,10 @@ 2016.1 - - - - + + + + diff --git a/system/ip/sja1000_1.0/hdl/can_ifc_axi_sync_duplex.v b/system/ip/sja1000_1.0/hdl/can_ifc_axi_sync_duplex.v index 580e3cd..72ed392 100644 --- a/system/ip/sja1000_1.0/hdl/can_ifc_axi_sync_duplex.v +++ b/system/ip/sja1000_1.0/hdl/can_ifc_axi_sync_duplex.v @@ -13,7 +13,7 @@ // Width of S_AXI data bus parameter integer C_S_AXI_DATA_WIDTH = 32, // Width of S_AXI address bus - parameter integer C_S_AXI_ADDR_WIDTH = 8 + parameter integer C_S_AXI_ADDR_WIDTH = 10 ) ( // Users to add ports here @@ -383,7 +383,8 @@ */ // Output register or memory read data - always @( posedge S_AXI_ACLK ) + // it is already registered in can_top_raw + always @*//( posedge S_AXI_ACLK ) begin if ( S_AXI_ARESETN == 1'b0 ) begin @@ -394,17 +395,19 @@ // When there is a valid read address (S_AXI_ARVALID) with // acceptance of read address by the slave (axi_arready), // output the read dada - if (slv_reg_rden) - begin + //if (slv_reg_rden) + //begin axi_rdata[7:0] <= reg_data_out_i; // register read data axi_rdata[C_S_AXI_DATA_WIDTH-1 : 8] <= 0; - end + //end + //else + //axi_rdata <= 0; end - end + end // Add user logic here - assign reg_addr_read_o = S_AXI_ARADDR; - assign reg_addr_write_o= S_AXI_AWADDR; + assign reg_addr_read_o = axi_araddr[ADDR_LSB+8-1 : ADDR_LSB]; + assign reg_addr_write_o= axi_awaddr[ADDR_LSB+8-1 : ADDR_LSB]; assign reg_rst_o = ~S_AXI_ARESETN; assign reg_re_o = slv_reg_rden; assign reg_we_o = slv_reg_wren; diff --git a/system/ip/sja1000_1.0/hdl/can_registers.v b/system/ip/sja1000_1.0/hdl/can_registers.v index 811f577..0a31f9c 100644 --- a/system/ip/sja1000_1.0/hdl/can_registers.v +++ b/system/ip/sja1000_1.0/hdl/can_registers.v @@ -1095,7 +1095,8 @@ always @ ( addr_read or extended_mode or mode or bus_timing_0 or bus_timing_1 or arbitration_lost_capture or rx_message_counter or mode_basic or error_capture_code ) begin - case({extended_mode, addr_read[4:0]}) /* synthesis parallel_case */ + //data_out = addr_read; // DBG + case({extended_mode, addr_read[4:0]}) // synthesis parallel_case {1'h1, 5'd00} : data_out = {4'b0000, mode_ext[3:1], mode[0]}; // extended mode {1'h1, 5'd01} : data_out = 8'h0; // extended mode {1'h1, 5'd02} : data_out = status; // extended mode diff --git a/system/ip/sja1000_1.0/hdl/sja1000.v b/system/ip/sja1000_1.0/hdl/sja1000.v index 679cba1..920650d 100644 --- a/system/ip/sja1000_1.0/hdl/sja1000.v +++ b/system/ip/sja1000_1.0/hdl/sja1000.v @@ -10,7 +10,7 @@ // Parameters of Axi Slave Bus Interface S00_AXI parameter integer C_S00_AXI_DATA_WIDTH = 32, - parameter integer C_S00_AXI_ADDR_WIDTH = 8 + parameter integer C_S00_AXI_ADDR_WIDTH = 16 // Parameters of Axi Slave Bus Interface S_AXI_INTR /* @@ -106,6 +106,7 @@ .reg_data_out_i(reg_data_out) ); + //assign reg_data_out = reg_addr_read; // DBG can_top_raw can_top_raw_inst ( .reg_we_i(reg_we), .reg_re_i(reg_re), diff --git a/system/script/dist.tcl b/system/script/dist.tcl new file mode 100644 index 0000000..f4f25e2 --- /dev/null +++ b/system/script/dist.tcl @@ -0,0 +1,22 @@ +# post-write_bitstream script +# executed in impl_1 directory + +#set dir [get_property DIRECTORY [current_project]] +#set impl_dir [get_property DIRECTORY [current_run]] +set _pwd [pwd] +set impl_dir . +set dir ../.. +puts "Current dir: $_pwd" +puts "Project dir: $dir" +puts "Impl dir: $impl_dir" +file copy -force $impl_dir/top_wrapper.hwdef $dir/../system.hdf +file copy -force $impl_dir/top_wrapper.bit $dir/../system.bit +file copy -force $dir/../system.hdf /tftpboot/system.hdf +file copy -force $dir/../system.bit /tftpboot/system.bit + +cd $dir/.. +exec bootgen -image system.bif -w -process_bitstream bin +cd $_pwd + +file copy -force $dir/../system.bit.bin /export/canbench/system.bit.bin +exec gzip -f /export/canbench/system.bit.bin diff --git a/system/script/recreate.tcl b/system/script/recreate.tcl index adcd4cb..32ad4f4 100644 --- a/system/script/recreate.tcl +++ b/system/script/recreate.tcl @@ -188,4 +188,6 @@ current_run -implementation [get_runs impl_1] check_ip_cache -import_from_project -use_project_cache +set_property STEPS.WRITE_BITSTREAM.TCL.POST $origin_dir/script/dist.tcl [get_runs impl_1] + puts "INFO: Project created:canbench" diff --git a/system/src/top/top.bd b/system/src/top/top.bd index ddb7b7c..3887d58 100644 --- a/system/src/top/top.bd +++ b/system/src/top/top.bd @@ -1,5 +1,5 @@  - + xilinx.com @@ -137,57 +137,51 @@ - CAN1_TXD + CAN2_RXD - out + in - CAN1_RXD + CAN3_RXD in - CAN2_TXD + CAN4_RXD + + in + + + + CAN1_TXD out - CAN2_RXD + CAN2_TXD - in + out - LED + CAN3_TXD out - - 7 - 0 - - KEY + CAN4_TXD - in - - 3 - 0 - + out - SW + CAN1_RXD in - - 7 - 0 - @@ -201,27 +195,33 @@ - CAN3_TXD - - out - - - - CAN4_TXD + LED out + + 7 + 0 + - CAN3_RXD + KEY in + + 3 + 0 + - CAN4_RXD + SW in + + 7 + 0 + @@ -234,6 +234,23 @@ top_imp 1.00.a + + canbench_cc_gpio_0 + + + top_canbench_cc_gpio_0_0 + + + + processing_system7_0_axi_periph + + + top_processing_system7_0_axi_periph_0 + 4 + 0 + xilinx.com:ip:axi_interconnect:2.1 + + processing_system7_0 @@ -445,15 +462,6 @@ clg400 - - processing_system7_0_axi_periph - - - top_processing_system7_0_axi_periph_0 - 2 - xilinx.com:ip:axi_interconnect:2.1 - - rst_processing_system7_0_100M @@ -462,18 +470,17 @@ - xlconstant_0 - + axi_test_0 + - top_xlconstant_0_0 - 0 + top_axi_test_0_0 - canbench_cc_gpio_0 - + xlconcat_0 + - top_canbench_cc_gpio_0_0 + top_xlconcat_0_0 @@ -485,6 +492,20 @@ 0x43C0FFFF + + sja1000_1 + + + top_sja1000_1_0 + + + + can_merge_0 + + + top_can_merge_0_0 + + @@ -497,6 +518,16 @@ + + processing_system7_0_axi_periph_M01_AXI + + + + + processing_system7_0_axi_periph_M03_AXI + + + @@ -504,12 +535,17 @@ - + + + + + + - - + + processing_system7_0_FCLK_RESET0_N @@ -519,10 +555,14 @@ rst_processing_system7_0_100M_peripheral_aresetn + + + - + + rst_processing_system7_0_100M_interconnect_aresetn @@ -555,44 +595,47 @@ - xlconstant_0_dout - - + xlconcat_0_dout + + - sja1000_0_can_tx - - + sja1000_0_irq + + - processing_system7_0_CAN0_PHY_TX - - + sja1000_1_irq + + - processing_system7_0_CAN1_PHY_TX - - + processing_system7_0_CAN0_PHY_TX + + - CAN1_RXD_1 - + can_merge_0_can_rx + + + + - CAN2_RXD_1 - - + processing_system7_0_CAN1_PHY_TX + + - CAN3_RXD_1 - - + sja1000_0_can_tx + + - sja1000_0_irq - - + sja1000_1_can_tx + + @@ -629,6 +672,18 @@ + + M02_AXI + + + + + + M03_AXI + + + + CLK.ACLK Clk @@ -666,7 +721,626 @@ - CLK.S00_ACLK + CLK.S00_ACLK + Clk + Clock + + + + + + + CLK + + + S00_ACLK + + + + + + ASSOCIATED_BUSIF + S00_AXI + + + + + + + + ASSOCIATED_RESET + S00_ARESETN + + + + + + + + + + RST.S00_ARESETN + Reset + Reset + + + + + + + RST + + + S00_ARESETN + + + + + + CLK.M00_ACLK + Clk + Clock + + + + + + + CLK + + + M00_ACLK + + + + + + ASSOCIATED_BUSIF + M00_AXI + + + + + + + + ASSOCIATED_RESET + M00_ARESETN + + + + + + + + + + RST.M00_ARESETN + Reset + Reset + + + + + + + RST + + + M00_ARESETN + + + + + + CLK.M01_ACLK + Clk + Clock + + + + + + + CLK + + + M01_ACLK + + + + + + ASSOCIATED_BUSIF + M01_AXI + + + + + + + + ASSOCIATED_RESET + M01_ARESETN + + + + + + + + + + RST.M01_ARESETN + Reset + Reset + + + + + + + RST + + + M01_ARESETN + + + + + + CLK.M02_ACLK + Clk + Clock + + + + + + + CLK + + + M02_ACLK + + + + + + ASSOCIATED_BUSIF + M02_AXI + + + + + + + + ASSOCIATED_RESET + M02_ARESETN + + + + + + + + + + RST.M02_ARESETN + Reset + Reset + + + + + + + RST + + + M02_ARESETN + + + + + + CLK.M03_ACLK + Clk + Clock + + + + + + + CLK + + + M03_ACLK + + + + + + ASSOCIATED_BUSIF + M03_AXI + + + + + + + + ASSOCIATED_RESET + M03_ARESETN + + + + + + + + + + RST.M03_ARESETN + Reset + Reset + + + + + + + RST + + + M03_ARESETN + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + ACLK + + in + + + + ARESETN + + in + + 0 + 0 + + + + + S00_ACLK + + in + + + + S00_ARESETN + + in + + 0 + 0 + + + + + M00_ACLK + + in + + + + M00_ARESETN + + in + + 0 + 0 + + + + + M01_ACLK + + in + + + + M01_ARESETN + + in + + 0 + 0 + + + + + M02_ACLK + + in + + + + M02_ARESETN + + in + + 0 + 0 + + + + + M03_ACLK + + in + + + + M03_ARESETN + + in + + 0 + 0 + + + + + + + + + xilinx.com + BlockDiagram/top_imp + processing_system7_0_axi_periph_imp + 1.00.a + + + xbar + + + top_xbar_0 + 1 + 4 + 0 + + + + s00_couplers + + + + m00_couplers + + + + m01_couplers + + + + m02_couplers + + + + m03_couplers + + + + + + s00_couplers_to_xbar + + + + + xbar_to_m00_couplers + + + + + xbar_to_m01_couplers + + + + + xbar_to_m02_couplers + + + + + xbar_to_m03_couplers + + + + + + + processing_system7_0_axi_periph_ACLK_net + + + + + + + + + + processing_system7_0_axi_periph_ARESETN_net + + + + + + + + + + S00_ACLK_1 + + + + + S00_ARESETN_1 + + + + + M00_ACLK_1 + + + + + M00_ARESETN_1 + + + + + M01_ACLK_1 + + + + + M01_ARESETN_1 + + + + + M02_ACLK_1 + + + + + M02_ARESETN_1 + + + + + M03_ACLK_1 + + + + + M03_ARESETN_1 + + + + + + + + + + + + + + + + + + + + + + + + + xilinx.com + BlockDiagram/top_imp/processing_system7_0_axi_periph_imp + m03_couplers + 1.00.a + + + M_AXI + + + + + + S_AXI + + + + + + CLK.M_ACLK + Clk + Clock + + + + + + + CLK + + + M_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXI + + + + + + + + ASSOCIATED_RESET + M_ARESETN + + + + + + + + + + RST.M_ARESETN + Reset + Reset + + + + + + + RST + + + M_ARESETN + + + + + + CLK.S_ACLK Clk Clock @@ -678,14 +1352,14 @@ CLK - S00_ACLK + S_ACLK ASSOCIATED_BUSIF - S00_AXI + S_AXI @@ -694,7 +1368,7 @@ ASSOCIATED_RESET - S00_ARESETN + S_ARESETN @@ -704,7 +1378,7 @@ - RST.S00_ARESETN + RST.S_ARESETN Reset Reset @@ -716,13 +1390,91 @@ RST - S00_ARESETN + S_ARESETN + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M_ACLK + + in + + + + M_ARESETN + + in + + 0 + 0 + + + + + S_ACLK + + in + + + + S_ARESETN + + in + + 0 + 0 + + + + + + + + + xilinx.com + BlockDiagram/top_imp/processing_system7_0_axi_periph_imp + m03_couplers_imp + 1.00.a + + + + + + + + + + + xilinx.com + BlockDiagram/top_imp/processing_system7_0_axi_periph_imp + m02_couplers + 1.00.a + + + M_AXI + + + + - CLK.M00_ACLK + S_AXI + + + + + + CLK.M_ACLK Clk Clock @@ -734,14 +1486,14 @@ CLK - M00_ACLK + M_ACLK ASSOCIATED_BUSIF - M00_AXI + M_AXI @@ -750,7 +1502,7 @@ ASSOCIATED_RESET - M00_ARESETN + M_ARESETN @@ -760,7 +1512,7 @@ - RST.M00_ARESETN + RST.M_ARESETN Reset Reset @@ -772,13 +1524,13 @@ RST - M00_ARESETN + M_ARESETN - CLK.M01_ACLK + CLK.S_ACLK Clk Clock @@ -790,14 +1542,14 @@ CLK - M01_ACLK + S_ACLK ASSOCIATED_BUSIF - M01_AXI + S_AXI @@ -806,7 +1558,7 @@ ASSOCIATED_RESET - M01_ARESETN + S_ARESETN @@ -816,7 +1568,7 @@ - RST.M01_ARESETN + RST.S_ARESETN Reset Reset @@ -828,7 +1580,7 @@ RST - M01_ARESETN + S_ARESETN @@ -839,50 +1591,18 @@ BlockDiagram :vivado.xilinx.com: - + - ACLK - - in - - - - ARESETN - - in - - 0 - 0 - - - - - S00_ACLK - - in - - - - S00_ARESETN - - in - - 0 - 0 - - - - - M00_ACLK + M_ACLK in - M00_ARESETN + M_ARESETN in @@ -892,13 +1612,13 @@ - M01_ACLK + S_ACLK in - M01_ARESETN + S_ARESETN in @@ -913,107 +1633,14 @@ xilinx.com - BlockDiagram/top_imp - processing_system7_0_axi_periph_imp + BlockDiagram/top_imp/processing_system7_0_axi_periph_imp + m02_couplers_imp 1.00.a - - - xbar - - - top_xbar_0 - 1 - 2 - 0 - - - - s00_couplers - - - - m00_couplers - - - - m01_couplers - - - - - - s00_couplers_to_xbar - - - - - xbar_to_m00_couplers - - - - - xbar_to_m01_couplers - - - - - - - processing_system7_0_axi_periph_ACLK_net - - - - - - - - processing_system7_0_axi_periph_ARESETN_net - - - - - - - - S00_ACLK_1 - - - - - S00_ARESETN_1 - - - - - M00_ACLK_1 - - - - - M00_ARESETN_1 - - - - - M01_ACLK_1 - - - - - M01_ARESETN_1 - - - - + + - - - - - - - - + + @@ -1624,11 +2251,23 @@ 4G 32 + + SEG_axi_test_0_S00_AXI_reg + /axi_test_0/S00_AXI/S00_AXI_reg + 0x43C10000 + 4K + SEG_sja1000_0_S00_AXI_reg /sja1000_0/S00_AXI/S00_AXI_reg 0x43C00000 - 64K + 4K + + + SEG_sja1000_1_S00_AXI_reg + /sja1000_1/S00_AXI/S00_AXI_reg + 0x43C30000 + 4K diff --git a/system/system.bif b/system/system.bif new file mode 100644 index 0000000..b57200c --- /dev/null +++ b/system/system.bif @@ -0,0 +1,4 @@ +all: +{ +system.bit +}