]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/commit
dcsimpledrv: mask write to unused bits of CR, STAT and PWM_PER registers.
authorPavel Pisa <pisa@cmp.felk.cvut.cz>
Wed, 26 Jul 2017 18:11:35 +0000 (20:11 +0200)
committerPavel Pisa <pisa@cmp.felk.cvut.cz>
Wed, 26 Jul 2017 18:11:35 +0000 (20:11 +0200)
commitf6f78117aac0aabca9d95915036df0d0098e7e8f
treee51e3e6924f93b25ca21d37b39045a3e281717d7
parent77e6c084121f8d099cf335cd093b7399d5406f99
dcsimpledrv: mask write to unused bits of CR, STAT and PWM_PER registers.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
system/ip/dcsimpledrv_1.0/hdl/dcsimpledrv_v1_0_S00_AXI.vhd