]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/commit
dcsimpledrv: add component for mapping FPGA_IO/PMOD1 and PMOD2 signals to dcsimpledrv.
authorPavel Pisa <pisa@cmp.felk.cvut.cz>
Tue, 25 Jul 2017 15:47:21 +0000 (17:47 +0200)
committerPavel Pisa <pisa@cmp.felk.cvut.cz>
Tue, 25 Jul 2017 15:47:21 +0000 (17:47 +0200)
commitc6643a3a08bf8579b015fc51c634ca8f9e0fdce6
treea2ce50651961461eaed7d29ac418056690149258
parent0e341ea1a146c458dc7fb965ccedb6a47b51d16d
dcsimpledrv: add component for mapping FPGA_IO/PMOD1 and PMOD2 signals to dcsimpledrv.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
system/ip/dcsimpledrv_to_pmod12_pins/component.xml [new file with mode: 0644]
system/ip/dcsimpledrv_to_pmod12_pins/dcsimpledrv_to_pmod12_pins.vhd [new file with mode: 0644]
system/ip/dcsimpledrv_to_pmod12_pins/xgui/dcsimpledrv_to_pmod12_pins_v1_0.tcl [new file with mode: 0644]