]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/commit
system: added GPIO IP
authorMartin Jerabek <jerabma7@fel.cvut.cz>
Thu, 12 May 2016 11:52:57 +0000 (13:52 +0200)
committerMartin Jerabek <jerabma7@fel.cvut.cz>
Thu, 12 May 2016 23:56:01 +0000 (01:56 +0200)
commit4413e7626dcc5a4512960c8693749832cc990e67
tree7fce56a9d1c0bbd1322fff950d0a96cb281a30a0
parent43f07deb5f98870fb8033ed4b609e4efc7333590
system: added GPIO IP
system/ip/canbench_cc_gpio/canbench_cc_gpio.vhd [new file with mode: 0644]
system/ip/canbench_cc_gpio/component.xml [new file with mode: 0644]
system/ip/canbench_cc_gpio/xgui/canbench_cc_gpio_v1_0.tcl [new file with mode: 0644]