X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/zynq/canbench-sw.git/blobdiff_plain/641288157a35046a2a4a2bd3beeb7e296b849cde..570de39169ecb20f86b073152234c55dc14d3787:/system/src/top/top.bd
diff --git a/system/src/top/top.bd b/system/src/top/top.bd
index 3887d58..2628992 100644
--- a/system/src/top/top.bd
+++ b/system/src/top/top.bd
@@ -469,13 +469,6 @@
top_rst_processing_system7_0_100M_0
-
- axi_test_0
-
-
- top_axi_test_0_0
-
-
xlconcat_0
@@ -500,10 +493,10 @@
- can_merge_0
-
+ can_crossbar_0
+
- top_can_merge_0_0
+ top_can_crossbar_0_0
@@ -518,16 +511,16 @@
-
- processing_system7_0_axi_periph_M01_AXI
-
-
-
processing_system7_0_axi_periph_M03_AXI
+
+ processing_system7_0_axi_periph_M02_AXI
+
+
+
@@ -535,7 +528,6 @@
-
@@ -546,6 +538,7 @@
+
processing_system7_0_FCLK_RESET0_N
@@ -555,7 +548,6 @@
rst_processing_system7_0_100M_peripheral_aresetn
-
@@ -563,6 +555,7 @@
+
rst_processing_system7_0_100M_interconnect_aresetn
@@ -612,30 +605,87 @@
processing_system7_0_CAN0_PHY_TX
-
-
-
- can_merge_0_can_rx
-
-
-
-
-
+
processing_system7_0_CAN1_PHY_TX
-
+
sja1000_0_can_tx
-
+
sja1000_1_can_tx
-
+
+
+
+ can_crossbar_0_ifc4_rx
+
+
+
+
+ can_crossbar_0_ifc3_rx
+
+
+
+
+ can_crossbar_0_ifc2_rx
+
+
+
+
+ can_crossbar_0_ifc1_rx
+
+
+
+
+ can_crossbar_0_can4_tx
+
+
+
+
+ can_crossbar_0_can3_tx
+
+
+
+
+ can_crossbar_0_can2_tx
+
+
+
+
+ can_crossbar_0_can1_tx
+
+
+
+
+ can_crossbar_0_can_stby
+
+
+
+
+ CAN1_RXD_1
+
+
+
+
+ CAN2_RXD_1
+
+
+
+
+ CAN3_RXD_1
+
+
+
+
+ CAN4_RXD_1
+
+
@@ -2251,12 +2301,6 @@
4G
32
-
- SEG_axi_test_0_S00_AXI_reg
- /axi_test_0/S00_AXI/S00_AXI_reg
- 0x43C10000
- 4K
-
SEG_sja1000_0_S00_AXI_reg
/sja1000_0/S00_AXI/S00_AXI_reg
@@ -2269,6 +2313,12 @@
0x43C30000
4K
+
+ SEG_can_crossbar_0_S00_AXI_reg
+ /can_crossbar_0/S00_AXI/S00_AXI_reg
+ 0x43C20000
+ 4K
+