]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/blobdiff - system/ip/axi_pwm_coprocessor_1.0/hdl/axi_pwm_coprocessor_v1_0.vhd
AXI PWM Coprocessor: remove AXI master part INIT_AXI_TXN signal from interface.
[fpga/zynq/canbench-sw.git] / system / ip / axi_pwm_coprocessor_1.0 / hdl / axi_pwm_coprocessor_v1_0.vhd
index a7e8024dc0a253ade8f13de04168242e56a5beed..fb219dcc62c51f67376939de87f93741a1c13396 100644 (file)
@@ -136,7 +136,6 @@ architecture arch_imp of axi_pwm_coprocessor_v1_0 is
                pwm_wr1 : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
                pwm_wr2 : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
 
-               INIT_AXI_TXN    : in std_logic;
                ERROR   : out std_logic;
                TXN_DONE        : out std_logic;
                M_AXI_ACLK      : in std_logic;