sja1000: tx_data register access de-parallelized (TOTEST)

[fpga/zynq/canbench-sw.git] / system / ip / sja1000_1.0 / hdl / can_top_raw.v

diff --git a/system/ip/sja1000_1.0/hdl/can_top_raw.v b/system/ip/sja1000_1.0/hdl/can_top_raw.v
index 546a598ca90d7cbdb079341b36d7727f2c30f40b..7bca79757949b8360d0e9f140320e20dd27fd237 100644 (file)
--- a/system/ip/sja1000_1.0/hdl/can_top_raw.v
+++ b/system/ip/sja1000_1.0/hdl/can_top_raw.v
@@ -353,6 +353,9 @@ wire   [7:0] tx_data_9;
 wire   [7:0] tx_data_10;
 wire   [7:0] tx_data_11;
 wire   [7:0] tx_data_12;
+
+wire   [7:0] tx_data;
+wire   [3:0] tx_data_addr;
 /* End: Tx data registers */
 
 /* Output signals from can_btl module */
@@ -676,19 +679,8 @@ can_bsp i_can_bsp
   /* End: This section is for EXTENDED mode */
 
   /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
-  .tx_data_0(tx_data_0),
-  .tx_data_1(tx_data_1),
-  .tx_data_2(tx_data_2),
-  .tx_data_3(tx_data_3),
-  .tx_data_4(tx_data_4),
-  .tx_data_5(tx_data_5),
-  .tx_data_6(tx_data_6),
-  .tx_data_7(tx_data_7),
-  .tx_data_8(tx_data_8),
-  .tx_data_9(tx_data_9),
-  .tx_data_10(tx_data_10),
-  .tx_data_11(tx_data_11),
-  .tx_data_12(tx_data_12),
+  .tx_data_addr_o(tx_data_addr),
+  .tx_data(tx_data),
   /* End: Tx data registers */
   
   /* Tx signal */
@@ -711,6 +703,9 @@ can_bsp i_can_bsp
 `endif
 );
 
+wire [7:0] tx_data_arr [12:0];
+assign tx_data_arr = {tx_data_12, tx_data_11, tx_data_10, tx_data_9, tx_data_8, tx_data_7, tx_data_6, tx_data_5, tx_data_4, tx_data_3, tx_data_2, tx_data_1, tx_data_0};
+assign tx_data = tx_data_arr[tx_data_addr]; // TODO: else xxx?
 
 
 // Multiplexing wb_dat_o from registers and rx fifo