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[fpga/zynq/canbench-sw.git] / system / ip / axi_pwm_coprocessor_1.0 / example_designs / bfm_design / design.tcl
1 proc create_ipi_design { offsetfile design_name } {
2         create_bd_design $design_name
3         open_bd_design $design_name
4
5         # Create Clock and Reset Ports
6         set ACLK [ create_bd_port -dir I -type clk ACLK ]
7         set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
8         set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
9         set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $ARESETN
10         set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
11
12         # Create instance: axi_pwm_coprocessor_0, and set properties
13         set axi_pwm_coprocessor_0 [ create_bd_cell -type ip -vlnv user.org:user:axi_pwm_coprocessor:1.0 axi_pwm_coprocessor_0]
14
15         # Create instance: master_0, and set properties
16         set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm master_0]
17         set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} ] $master_0
18
19         # Create interface connections
20         connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI_LITE] [get_bd_intf_pins axi_pwm_coprocessor_0/S00_AXI]
21
22         # Create port connections
23         connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/M_AXI_LITE_ACLK] [get_bd_pins axi_pwm_coprocessor_0/S00_AXI_ACLK]
24         connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/M_AXI_LITE_ARESETN] [get_bd_pins axi_pwm_coprocessor_0/S00_AXI_ARESETN]
25
26         # Create External ports
27         set M00_AXI_INIT_AXI_TXN [ create_bd_port -dir I M00_AXI_INIT_AXI_TXN ]
28         set M00_AXI_ERROR [ create_bd_port -dir O M00_AXI_ERROR ]
29         set M00_AXI_TXN_DONE [ create_bd_port -dir O M00_AXI_TXN_DONE ]
30
31         # Create instance: slave_0, and set properties
32         set slave_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm slave_0]
33         set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} CONFIG.C_MODE_SELECT {1} CONFIG.C_S_AXI4_LITE_HIGHADDR {0x4000FFFF} CONFIG.C_S_AXI4_BASEADDR {0x40000000} CONFIG.C_S_AXI4_LITE_MEMORY_MODEL_MODE {1} ] $slave_0
34
35 connect_bd_intf_net [get_bd_intf_pins slave_0/S_AXI_LITE] [get_bd_intf_pins axi_pwm_coprocessor_0/M00_AXI]
36         # Create port connections
37         connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins slave_0/S_AXI_LITE_ACLK] [get_bd_pins axi_pwm_coprocessor_0/M00_AXI_ACLK]
38         connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins slave_0/S_AXI_LITE_ARESETN] [get_bd_pins axi_pwm_coprocessor_0/M00_AXI_ARESETN]
39         connect_bd_net -net init_axi_txn_00 [get_bd_ports M00_AXI_INIT_AXI_TXN] [get_bd_pins axi_pwm_coprocessor_0/M00_AXI_INIT_AXI_TXN]
40         connect_bd_net -net error_00 [get_bd_ports M00_AXI_ERROR] [get_bd_pins axi_pwm_coprocessor_0/M00_AXI_ERROR]
41         connect_bd_net -net txn_done_00 [get_bd_ports M00_AXI_TXN_DONE] [get_bd_pins axi_pwm_coprocessor_0/M00_AXI_TXN_DONE]
42
43         # Auto assign address
44         assign_bd_address
45
46         # Copy all address to interface_address.vh file
47         set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
48         upvar 1 $offsetfile offset_file
49         set offset_file "${bd_path}/axi_pwm_coprocessor_v1_0_tb_include.vh"
50         set fp [open $offset_file "w"]
51         puts $fp "`ifndef axi_pwm_coprocessor_v1_0_tb_include_vh_"
52         puts $fp "`define axi_pwm_coprocessor_v1_0_tb_include_vh_\n"
53         puts $fp "//Configuration current bd names"
54         puts $fp "`define BD_INST_NAME ${design_name}_i"
55         puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
56         puts $fp "//Configuration address parameters"
57
58         set offset [get_property OFFSET [get_bd_addr_segs -of_objects [get_bd_addr_spaces master_0/Data_lite]]]
59         set offset_hex [string replace $offset 0 1 "32'h"]
60         puts $fp "`define S00_AXI_SLAVE_ADDRESS ${offset_hex}"
61
62         puts $fp "`endif"
63         close $fp
64 }
65
66 set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:axi_pwm_coprocessor:1.0]]]]
67 set test_bench_file ${ip_path}/example_designs/bfm_design/axi_pwm_coprocessor_v1_0_tb.v
68 set interface_address_vh_file ""
69
70 # Set IP Repository and Update IP Catalogue 
71 set repo_paths [get_property ip_repo_paths [current_fileset]] 
72 if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
73         set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
74         update_ip_catalog
75 }
76
77 set design_name ""
78 set all_bd {}
79 set all_bd_files [get_files *.bd -quiet]
80 foreach file $all_bd_files {
81 set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
82 set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
83 lappend all_bd $bd_name
84 }
85
86 for { set i 1 } { 1 } { incr i } {
87         set design_name "axi_pwm_coprocessor_v1_0_bfm_${i}"
88         if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
89                 break
90         }
91 }
92
93 create_ipi_design interface_address_vh_file ${design_name}
94 validate_bd_design
95
96 set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
97 import_files -force -norecurse $wrapper_file
98
99 set_property SOURCE_SET sources_1 [get_filesets sim_1]
100 import_files -fileset sim_1 -norecurse -force $test_bench_file
101 remove_files -quiet -fileset sim_1 axi_pwm_coprocessor_v1_0_tb_include.vh
102 import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
103 set_property top axi_pwm_coprocessor_v1_0_tb [get_filesets sim_1]
104 set_property top_lib {} [get_filesets sim_1]
105 set_property top_file {} [get_filesets sim_1]
106 launch_xsim -simset sim_1 -mode behavioral
107 restart
108 run 1000 us