]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-hw.git/commit
layout: finished routing
authorMartin Jerabek <jerabma7@fel.cvut.cz>
Thu, 21 Apr 2016 19:13:46 +0000 (21:13 +0200)
committerMartin Jerabek <jerabma7@fel.cvut.cz>
Thu, 21 Apr 2016 19:13:46 +0000 (21:13 +0200)
commitc7e72401970d4b590c8012d96ddd67e84039fb31
treeee22a3b7ea6db8d902a144e6aaa22cda16f1d374
parent5316287fadb4d86bb645aa6f0952afd428a70d37
layout: finished routing
canbench-hw.kicad_pcb
jx1.sch