]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-hw.git/commit
optional common CAN termination, debouncing capacitors only 10nF, footprints
authorMartin Jerabek <jerabma7@fel.cvut.cz>
Mon, 11 Apr 2016 23:03:47 +0000 (01:03 +0200)
committerMartin Jerabek <jerabma7@fel.cvut.cz>
Mon, 11 Apr 2016 23:03:47 +0000 (01:03 +0200)
commit74c526a15116845e5e7151efa1e8eb3ad179ea48
tree4e94e8b260aac92adef8bc7f6ae7c367379851ca
parent5ac25cb9659f0ff46de94aa49f73e6e06078bc53
optional common CAN termination, debouncing capacitors only 10nF, footprints
can.sch
canbench-hw.sch
jx1.sch
jx2.sch
lib/footprints.pretty/DC_Jack_Socket_THT.kicad_mod [new file with mode: 0644]
power.sch
user-io.sch