]> rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/history - openMSP430_uart.prj
projects / fpga / virtex2 / uart.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
+ README
[fpga/virtex2/uart.git] / openMSP430_uart.prj
2011-02-13 Vladimir Burian+ PWM output capability. blob | commitdiff | raw
2011-02-04 Vladimir BurianConnection of HW UART peripheral blob | commitdiff | raw | diff to current
2011-01-10 Vladimir BurianPeripheral connected to the quadcount module and an... blob | commitdiff | raw | diff to current
2011-01-10 Vladimir BurianAdded custom openMSP430 peripheral as an interface... blob | commitdiff | raw | diff to current
2011-01-09 Vladimir BurianCopied all needed files. blob | commitdiff | raw | diff to current
MSP430 simple UART echo - test top level design for Virtex 2 V2MB1000 board