From: Vladimir Burian Date: Fri, 4 Feb 2011 19:41:16 +0000 (+0100) Subject: Connection of HW UART peripheral X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/virtex2/uart.git/commitdiff_plain/18168561d4ba83c72a2bb46379eed51551045138 Connection of HW UART peripheral Peripherals of SW UART (GPIO and TimerA) were exchanged by HW UART peripheral. --- diff --git a/openMSP430_uart.prj b/openMSP430_uart.prj index d132214..5d3418b 100644 --- a/openMSP430_uart.prj +++ b/openMSP430_uart.prj @@ -16,8 +16,13 @@ verilog work openmsp430/timescale.v verilog work openMSP430_defines.v -verilog work openmsp430/periph/omsp_gpio.v -verilog work openmsp430/periph/omsp_timerA.v +vhdl work uart/tx_control.vhd +vhdl work uart/tx.vhd +vhdl work uart/rx_control.vhd +vhdl work uart/rx.vhd +vhdl work uart/fifo.vhd +vhdl work uart/baud_gen.vhd +vhdl work uart/uart.vhd vhdl work omsp_quadcount.vhd vhdl work quadcount/dff.vhdl diff --git a/openMSP430_uart.vhd b/openMSP430_uart.vhd index eafcbc8..d742fe2 100644 --- a/openMSP430_uart.vhd +++ b/openMSP430_uart.vhd @@ -77,86 +77,6 @@ architecture rtl of openMSP430_uart is ); end component; - - component omsp_gpio - generic ( - P1_EN : std_logic; - P2_EN : std_logic; - P3_EN : std_logic; - P4_EN : std_logic; - P5_EN : std_logic; - P6_EN : std_logic - ); - port( - mclk : in std_logic; - p1_din : in std_logic_vector(7 downto 0); - p2_din : in std_logic_vector(7 downto 0); - p3_din : in std_logic_vector(7 downto 0); - p4_din : in std_logic_vector(7 downto 0); - p5_din : in std_logic_vector(7 downto 0); - p6_din : in std_logic_vector(7 downto 0); - per_addr : in std_logic_vector(7 downto 0); - per_din : in std_logic_vector(15 downto 0); - per_en : in std_logic; - per_wen : in std_logic_vector(1 downto 0); - puc : in std_logic; - irq_port1 : out std_logic; - irq_port2 : out std_logic; - p1_dout : out std_logic_vector(7 downto 0); - p1_dout_en : out std_logic_vector(7 downto 0); - p1_sel : out std_logic_vector(7 downto 0); - p2_dout : out std_logic_vector(7 downto 0); - p2_dout_en : out std_logic_vector(7 downto 0); - p2_sel : out std_logic_vector(7 downto 0); - p3_dout : out std_logic_vector(7 downto 0); - p3_dout_en : out std_logic_vector(7 downto 0); - p3_sel : out std_logic_vector(7 downto 0); - p4_dout : out std_logic_vector(7 downto 0); - p4_dout_en : out std_logic_vector(7 downto 0); - p4_sel : out std_logic_vector(7 downto 0); - p5_dout : out std_logic_vector(7 downto 0); - p5_dout_en : out std_logic_vector(7 downto 0); - p5_sel : out std_logic_vector(7 downto 0); - p6_dout : out std_logic_vector(7 downto 0); - p6_dout_en : out std_logic_vector(7 downto 0); - p6_sel : out std_logic_vector(7 downto 0); - per_dout : out std_logic_vector(15 downto 0) - ); - end component; - - component omsp_timerA - port ( - irq_ta0 : out std_logic; -- Timer A interrupt: TACCR0 - irq_ta1 : out std_logic; -- Timer A interrupt: TAIV, TACCR1, TACCR2 - per_dout : out std_logic_vector (15 downto 0); -- Peripheral data output - ta_out0 : out std_logic; -- Timer A output 0 - ta_out0_en : out std_logic; -- Timer A output 0 enable - ta_out1 : out std_logic; -- Timer A output 1 - ta_out1_en : out std_logic; -- Timer A output 1 enable - ta_out2 : out std_logic; -- Timer A output 2 - ta_out2_en : out std_logic; -- Timer A output 2 enable - - aclk_en : in std_logic; -- ACLK enable (from CPU) - dbg_freeze : in std_logic; -- Freeze Timer A counter - inclk : in std_logic; -- INCLK external timer clock (SLOW) - irq_ta0_acc : in std_logic; -- Interrupt request TACCR0 accepted - mclk : in std_logic; -- Main system clock - per_addr : in std_logic_vector (7 downto 0); -- Peripheral address - per_din : in std_logic_Vector (15 downto 0); -- Peripheral data input - per_en : in std_logic; -- Peripheral enable (high active) - per_wen : in std_logic_vector (1 downto 0); -- Peripheral write enable (high active) - puc : in std_logic; -- Main system reset - smclk_en : in std_logic; -- SMCLK enable (from CPU) - ta_cci0a : in std_logic; -- Timer A capture 0 input A - ta_cci0b : in std_logic; -- Timer A capture 0 input B - ta_cci1a : in std_logic; -- Timer A capture 1 input A - ta_cci1b : in std_logic; -- Timer A capture 1 input B - ta_cci2a : in std_logic; -- Timer A capture 2 input A - ta_cci2b : in std_logic; -- Timer A capture 2 input B - taclk : in std_logic -- TACLK external timer clock (SLOW) - ); - end component; - component omsp_quadcount is port ( mclk : in std_logic; @@ -172,6 +92,23 @@ architecture rtl of openMSP430_uart is qcount : in std_logic_vector (31 downto 0) ); end component; + + component uart is + port ( + mclk : in std_logic; + per_addr : in std_logic_vector (7 downto 0); + per_din : in std_logic_vector (15 downto 0); + per_en : in std_logic; + per_wen : in std_logic_vector (1 downto 0); + puc : in std_logic; + per_irq_acc : in std_logic; + per_irq : out std_logic; + per_dout : out std_logic_vector (15 downto 0); + + rxd : in std_logic; + txd : out std_logic + ); + end component; component qcounter is port ( @@ -210,13 +147,11 @@ architecture rtl of openMSP430_uart is signal per_addr : std_logic_vector (7 downto 0); - signal gpio_per_dout : std_logic_vector (15 downto 0); - signal timerA_per_dout : std_logic_vector (15 downto 0); signal omsp_quadcount_dout : std_logic_vector (15 downto 0); + signal omsp_quadcount_irq : std_logic; - signal irq_ta0 : std_logic; - signal irq_ta1 : std_logic; - signal omsp_quadcount_irq : std_logic; + signal uart_dout : std_logic_vector (15 downto 0); + signal uart_irq : std_logic; signal qcount : std_logic_vector (31 downto 0); @@ -291,85 +226,6 @@ begin we => '1' ); - - omsp_gpio_0 : omsp_gpio - generic map ( - P1_EN => '1', -- Enable Port 1 - P2_EN => '1', -- Enable Port 2 - P3_EN => '0', -- Enable Port 3 - P4_EN => '0', -- Enable Port 4 - P5_EN => '0', -- Enable Port 5 - P6_EN => '0' -- Enable Port 6 - ) - port map ( - irq_port1 => open, - irq_port2 => open, - p1_dout (7 downto 2) => open, - p1_dout (1) => RXD, - p1_dout (0) => open, - p1_dout_en => open, - p1_sel => open, - p2_dout => open, - p2_dout_en => open, - p2_sel => open, - p3_dout => open, - p3_dout_en => open, - p3_sel => open, - p4_dout => open, - p4_dout_en => open, - p4_sel => open, - p5_dout => open, - p5_dout_en => open, - p5_sel => open, - p6_dout => open, - p6_dout_en => open, - p6_sel => open, - per_dout => gpio_per_dout, - mclk => mclk, - p1_din => (others => '0'), - p2_din => (others => '0'), - p3_din => (others => '0'), - p4_din => (others => '0'), - p5_din => (others => '0'), - p6_din => (others => '0'), - per_addr => per_addr, - per_din => per_din, - per_en => per_en, - per_wen => per_wen, - puc => puc - ); - - omsp_timerA_0 : omsp_timerA port map ( - irq_ta0 => irq_ta0, - irq_ta1 => irq_ta1, - per_dout => timerA_per_dout, - ta_out0 => open, - ta_out0_en => open, - ta_out1 => open, - ta_out1_en => open, - ta_out2 => open, - ta_out2_en => open, - - aclk_en => aclk_en, - dbg_freeze => '0', - inclk => '0', - irq_ta0_acc => irq_acc (9), - mclk => mclk, - per_addr => per_addr, - per_din => per_din, - per_en => per_en, - per_wen => per_wen, - puc => puc, - smclk_en => smclk_en, - ta_cci0a => '0', - ta_cci0b => TXD, - ta_cci1a => '0', - ta_cci1b => '0', - ta_cci2a => '0', - ta_cci2b => '0', - taclk => '0' - ); - omsp_quadcount_0 : omsp_quadcount port map ( mclk => mclk, per_addr => per_addr, @@ -384,6 +240,21 @@ begin qcount => qcount ); + uart_o : uart port map ( + mclk => mclk, + per_addr => per_addr, + per_din => per_din, + per_en => per_en, + per_wen => per_wen, + puc => puc, + per_irq_acc => '0', + per_irq => uart_irq, + per_dout => uart_dout, + + rxd => TXD, + txd => RXD + ); + qcounter_0 : qcounter port map ( clock => mclk, reset => ROT_PRESS, @@ -400,10 +271,9 @@ begin -------------------------------------------------------------------------------- - per_dout <= gpio_per_dout or timerA_per_dout or omsp_quadcount_dout; + per_dout <= uart_dout or omsp_quadcount_dout; - irq <= (9 => irq_ta0, - 8 => irq_ta1, + irq <= (6 => uart_irq, 7 => omsp_quadcount_irq, others => '0');