projects / fpga / virtex2 / uart.git / commit
| author | Vladimir Burian <buriavl2@fel.cvut.cz> | |
| Mon, 10 Jan 2011 10:45:46 +0000 (11:45 +0100) | ||
| committer | Vladimir Burian <buriavl2@fel.cvut.cz> | |
| Mon, 10 Jan 2011 10:45:46 +0000 (11:45 +0100) | ||
| commit | 0310188691edf68ef4c517d7171217adf7d3af50 | |
| tree | 6c9c0ab29670e0219a2d9b77c0b24001a95b9c92 | tree | snapshot |
| parent | 142ab6f87c742147b6ac18495f17f8f1b9b528bb | commit | diff |
| .gitmodules | diff | blob | history | |
| quadcount | [new submodule] | blob |