X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/virtex2/uart.git/blobdiff_plain/5793e4aff64fad0fe712536bf9c7c385dcd82fa8..becb341a3d46f3a6458ce87a4f531f81e03e84b2:/openMSP430_uart.vhd

diff --git a/openMSP430_uart.vhd b/openMSP430_uart.vhd
index 27c4acc..bdd92f6 100644
--- a/openMSP430_uart.vhd
+++ b/openMSP430_uart.vhd
@@ -8,8 +8,8 @@ entity openMSP430_uart is
     CLK_24MHz: in std_logic;
     RESET: in std_logic;
 
-    RXD : out std_logic;
-    TXD : in std_logic;
+    RXD : in std_logic;
+    TXD : out std_logic;
     
     ROT_FEED : out std_logic;
     ROT_A : in std_logic;
@@ -242,8 +242,8 @@ begin
     per_irq     => uart_irq,
     per_dout    => uart_dout,
 
-    rxd         => TXD,
-    txd         => RXD
+    rxd         => RXD,
+    txd         => TXD
   );