X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/virtex2/uart.git/blobdiff_plain/04325406ee353e690bad026b6961ed6331c1ab0d..a24f1edd0b700eb64b3e56835af9a69f926ac0d6:/coregen/rom_8x2k.vho

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+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component rom_8x2k
+	port (
+	addr: IN std_logic_VECTOR(10 downto 0);
+	clk: IN std_logic;
+	din: IN std_logic_VECTOR(7 downto 0);
+	dout: OUT std_logic_VECTOR(7 downto 0);
+	en: IN std_logic;
+	we: IN std_logic);
+end component;
+
+-- Synplicity black box declaration
+attribute syn_black_box : boolean;
+attribute syn_black_box of rom_8x2k: component is true;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : rom_8x2k
+		port map (
+			addr => addr,
+			clk => clk,
+			din => din,
+			dout => dout,
+			en => en,
+			we => we);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file rom_8x2k.vhd when simulating
+-- the core, rom_8x2k. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+