+ README

[fpga/virtex2/uart.git] / openMSP430_uart.prj

diff --git a/openMSP430_uart.prj b/openMSP430_uart.prj
index 8da597078b672028f3fa9a65b07b5f9895c7758f..6d4283c5d0311e67dce816d44e90c25f14ec232a 100644 (file)
--- a/openMSP430_uart.prj
+++ b/openMSP430_uart.prj
@@ -16,10 +16,20 @@ verilog work openmsp430/timescale.v
 
 verilog work openMSP430_defines.v
 
-verilog work openmsp430/periph/omsp_gpio.v
-verilog work openmsp430/periph/omsp_timerA.v
+vhdl work uart/tx_control.vhd
+vhdl work uart/tx.vhd
+vhdl work uart/rx_control.vhd
+vhdl work uart/rx.vhd
+vhdl work uart/fifo.vhd
+vhdl work uart/baud_gen.vhd
+vhdl work uart/uart.vhd
+
+vhdl work counter.vhd
+vhdl work omsp_pwm.vhd
 
 vhdl work omsp_quadcount.vhd
+vhdl work quadcount/dff.vhdl
+vhdl work quadcount/qcounter.vhdl
 
 vhdl work coregen/ram_8x512.vhd
 vhdl work coregen/rom_8x2k.vhd