+ PWM output capability.

[fpga/virtex2/uart.git] / openMSP430_uart.vhd

diff --git a/openMSP430_uart.vhd b/openMSP430_uart.vhd
index bdd92f6c764508fecc6713f9938c8b9b55959141..7537c6f64c7e9f7cf3eb4915f3968f5a8faa9af6 100644 (file)
--- a/openMSP430_uart.vhd
+++ b/openMSP430_uart.vhd
@@ -14,7 +14,9 @@ entity openMSP430_uart is
     ROT_FEED : out std_logic;
     ROT_A : in std_logic;
     ROT_B : in std_logic;
-    ROT_PRESS : in std_logic
+    ROT_PRESS : in std_logic;
+
+    PWM : out std_logic
   );
 end openMSP430_uart;
 
@@ -110,6 +112,33 @@ architecture rtl of openMSP430_uart is
     );
   end component;
 
+  component omsp_pwm is
+    generic (
+      ADDR      : integer;
+      PWM_WIDTH : integer);
+    port (
+      mclk     : in  std_logic;
+      puc      : in  std_logic;
+      per_addr : in  std_logic_vector (7 downto 0);
+      per_en   : in  std_logic;
+      per_wen  : in  std_logic_vector (1 downto 0);
+      per_din  : in  std_logic_vector (15 downto 0);
+      per_dout : out std_logic_vector (15 downto 0);
+      pwm_cnt  : in  std_logic_vector (15 downto 0);
+      pwm      : out std_logic);
+  end component omsp_pwm;
+
+  component counter is
+    generic (
+      WIDTH : integer;
+      MAX   : integer);
+    port (
+      clk   : in  std_logic;
+      reset : in  std_ulogic;
+      count : out std_logic_vector (WIDTH-1 downto 0));
+  end component counter;
+  
+  
 
   signal mclk : std_logic;
   signal puc : std_logic;
@@ -142,6 +171,9 @@ architecture rtl of openMSP430_uart is
   signal uart_dout : std_logic_vector (15 downto 0);
   signal uart_irq  : std_logic;
 
+  signal omsp_pwm_dout : std_logic_vector (15 downto 0);
+
+  signal pwm_cnt : std_logic_vector (15 downto 0);
 
 --------------------------------------------------------------------------------
 
@@ -246,10 +278,33 @@ begin
     txd         => TXD
   );
 
+  omsp_pwm_1 : omsp_pwm
+    generic map (
+      ADDR      => 16#0160#,
+      PWM_WIDTH => 16)
+    port map (
+      mclk     => mclk,
+      puc      => puc,
+      per_addr => per_addr,
+      per_en   => per_en,
+      per_wen  => per_wen,
+      per_din  => per_din,
+      per_dout => omsp_pwm_dout,
+      pwm_cnt  => pwm_cnt,
+      pwm      => PWM);
 
+  counter_1 : counter
+    generic map (
+      WIDTH => 16,
+      MAX   => 2**16 - 2)
+    port map (
+      clk   => mclk,
+      reset => puc,
+      count => pwm_cnt);
+  
 --------------------------------------------------------------------------------
 
-  per_dout <= uart_dout or omsp_quadcount_dout;
+  per_dout <= uart_dout or omsp_quadcount_dout or omsp_pwm_dout;
   
   irq <= (6 => uart_irq,
           7 => omsp_quadcount_irq,