+ PWM output capability.

[fpga/virtex2/uart.git] / openMSP430_uart.prj

diff --git a/openMSP430_uart.prj b/openMSP430_uart.prj
index 5d3418bd2bd7ff6e4d8b7cb646b081a70a6a2015..6d4283c5d0311e67dce816d44e90c25f14ec232a 100644 (file)
--- a/openMSP430_uart.prj
+++ b/openMSP430_uart.prj
@@ -24,6 +24,9 @@ vhdl work uart/fifo.vhd
 vhdl work uart/baud_gen.vhd
 vhdl work uart/uart.vhd
 
+vhdl work counter.vhd
+vhdl work omsp_pwm.vhd
+
 vhdl work omsp_quadcount.vhd
 vhdl work quadcount/dff.vhdl
 vhdl work quadcount/qcounter.vhdl