library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity openMSP430_uart is port ( CLK_24MHz: in std_logic; RESET: in std_logic; RXD : in std_logic; TXD : out std_logic; ROT_FEED : out std_logic; ROT_A : in std_logic; ROT_B : in std_logic; ROT_PRESS : in std_logic; PWM : out std_logic ); end openMSP430_uart; -------------------------------------------------------------------------------- architecture rtl of openMSP430_uart is component openMSP430 is port( aclk_en : out std_logic; -- ACLK enable dbg_freeze : out std_logic; -- Freeze peripherals dbg_uart_txd : out std_logic; -- Debug interface: UART TXD dmem_addr : out std_logic_vector (8 downto 0); -- Data Memory address dmem_cen : out std_logic; -- Data Memory chip enable (low active) dmem_din : out std_logic_vector (15 downto 0); -- Data Memory data input dmem_wen : out std_logic_vector (1 downto 0); -- Data Memory write enable (low active) irq_acc : out std_logic_vector (13 downto 0); -- Interrupt request accepted (one-hot signal) mclk : out std_logic; -- Main system clock per_addr : out std_logic_vector (7 downto 0); -- Peripheral address per_din : out std_logic_vector (15 downto 0); -- Peripheral data input per_wen : out std_logic_vector (1 downto 0); -- Peripheral write enable (high active) per_en : out std_logic; -- Peripheral enable (high active) pmem_addr : out std_logic_vector (10 downto 0); -- Program Memory address pmem_cen : out std_logic; -- Program Memory chip enable (low active) pmem_din : out std_logic_vector (15 downto 0); -- Program Memory data input (optional) pmem_wen : out std_logic_vector (1 downto 0); -- Program Memory write enable (low active) (optional) puc : out std_logic; -- Main system reset smclk_en : out std_logic; -- SMCLK enable dbg_uart_rxd : in std_logic; -- Debug interface: UART RXD dco_clk : in std_logic; -- Fast oscillator (fast clock) dmem_dout : in std_logic_vector (15 downto 0); -- Data Memory data output irq : in std_logic_vector (13 downto 0); -- Maskable interrupts lfxt_clk : in std_logic; -- Low frequency oscillator (typ 32kHz) nmi : in std_logic; -- Non-maskable interrupt (asynchronous) per_dout : in std_logic_vector (15 downto 0); -- Peripheral data output pmem_dout : in std_logic_vector (15 downto 0); -- Program Memory data output reset_n : in std_logic -- Reset Pin (low active) ); end component; component ram_8x512 port ( addr: in std_logic_VECTOR(8 downto 0); clk: in std_logic; din: in std_logic_VECTOR(7 downto 0); dout: out std_logic_VECTOR(7 downto 0); en: in std_logic; we: in std_logic ); end component; component rom_8x2k port ( addr: in std_logic_VECTOR(10 downto 0); clk: in std_logic; din: in std_logic_VECTOR(7 downto 0); dout: out std_logic_VECTOR(7 downto 0); en: in std_logic; we: in std_logic ); end component; component omsp_quadcount is generic ( ADDR : std_logic_vector (15 downto 0)); port ( mclk : in std_logic; puc : in std_logic; per_addr : in std_logic_vector (7 downto 0); per_en : in std_logic; per_irq : out std_logic; per_dout : out std_logic_vector (15 downto 0); qclk : in std_logic; qreset : in std_logic; a0, b0 : in std_logic; qcount : out std_logic_vector (31 downto 0)); end component omsp_quadcount; component uart is port ( mclk : in std_logic; per_addr : in std_logic_vector (7 downto 0); per_din : in std_logic_vector (15 downto 0); per_en : in std_logic; per_wen : in std_logic_vector (1 downto 0); puc : in std_logic; per_irq_acc : in std_logic; per_irq : out std_logic; per_dout : out std_logic_vector (15 downto 0); rxd : in std_logic; txd : out std_logic ); end component; component omsp_pwm is generic ( ADDR : integer; PWM_WIDTH : integer); port ( mclk : in std_logic; puc : in std_logic; per_addr : in std_logic_vector (7 downto 0); per_en : in std_logic; per_wen : in std_logic_vector (1 downto 0); per_din : in std_logic_vector (15 downto 0); per_dout : out std_logic_vector (15 downto 0); pwm_cnt : in std_logic_vector (15 downto 0); pwm : out std_logic); end component omsp_pwm; component counter is generic ( WIDTH : integer; MAX : integer); port ( clk : in std_logic; reset : in std_ulogic; count : out std_logic_vector (WIDTH-1 downto 0)); end component counter; signal mclk : std_logic; signal puc : std_logic; signal aclk_en : std_logic; signal smclk_en : std_logic; signal irq_acc : std_logic_vector (13 downto 0); signal irq : std_logic_vector (13 downto 0); signal pmem_addr : std_logic_vector (10 downto 0); signal pmem_dout : std_logic_vector (15 downto 0); signal pmem_cen : std_logic; signal dmem_addr : std_logic_vector (8 downto 0); signal dmem_cen : std_logic; signal dmem_wen : std_logic_vector (1 downto 0); signal dmem_din : std_logic_vector (15 downto 0); signal dmem_dout : std_logic_vector (15 downto 0); signal per_din : std_logic_vector (15 downto 0); signal per_dout : std_logic_Vector (15 downto 0); signal per_wen : std_logic_vector (1 downto 0); signal per_en : std_logic; signal per_addr : std_logic_vector (7 downto 0); signal omsp_quadcount_dout : std_logic_vector (15 downto 0); signal omsp_quadcount_irq : std_logic; signal uart_dout : std_logic_vector (15 downto 0); signal uart_irq : std_logic; signal omsp_pwm_dout : std_logic_vector (15 downto 0); signal pwm_cnt : std_logic_vector (15 downto 0); -------------------------------------------------------------------------------- begin openMSP430_0 : openMSP430 port map ( aclk_en => aclk_en, dbg_freeze => open, dbg_uart_txd => open, dmem_addr => dmem_addr, dmem_cen => dmem_cen, dmem_din => dmem_din, dmem_wen => dmem_wen, irq_acc => irq_acc, mclk => mclk, per_addr => per_addr, per_din => per_din, per_wen => per_wen, per_en => per_en, pmem_addr => pmem_addr, pmem_cen => pmem_cen, pmem_din => open, pmem_wen => open, puc => puc, smclk_en => smclk_en, dbg_uart_rxd => '0', dco_clk => CLK_24MHz, dmem_dout => dmem_dout, irq => irq, lfxt_clk => '0', nmi => '0', per_dout => per_dout, pmem_dout => pmem_dout, reset_n => RESET ); ram_8x512_hi : ram_8x512 port map ( addr => dmem_addr, clk => mclk, din => dmem_din (15 downto 8), dout => dmem_dout (15 downto 8), en => dmem_cen, we => dmem_wen (1) ); ram_8x512_lo : ram_8x512 port map ( addr => dmem_addr, clk => mclk, din => dmem_din (7 downto 0), dout => dmem_dout (7 downto 0), en => dmem_cen, we => dmem_wen (0) ); rom_8x2k_hi : rom_8x2k port map ( addr => pmem_addr, clk => mclk, din => (others => '0'), dout => pmem_dout (15 downto 8), en => pmem_cen, we => '1' ); rom_8x2k_lo : rom_8x2k port map ( addr => pmem_addr, clk => mclk, din => (others => '0'), dout => pmem_dout (7 downto 0), en => pmem_cen, we => '1' ); omsp_quadcount_1: omsp_quadcount generic map ( ADDR => X"0150") port map ( mclk => mclk, puc => puc, per_addr => per_addr, per_en => per_en, per_irq => omsp_quadcount_irq, per_dout => omsp_quadcount_dout, qclk => mclk, qreset => ROT_PRESS, a0 => ROT_A, b0 => ROT_B, qcount => open ); uart_o : uart port map ( mclk => mclk, per_addr => per_addr, per_din => per_din, per_en => per_en, per_wen => per_wen, puc => puc, per_irq_acc => '0', per_irq => uart_irq, per_dout => uart_dout, rxd => RXD, txd => TXD ); omsp_pwm_1 : omsp_pwm generic map ( ADDR => 16#0160#, PWM_WIDTH => 16) port map ( mclk => mclk, puc => puc, per_addr => per_addr, per_en => per_en, per_wen => per_wen, per_din => per_din, per_dout => omsp_pwm_dout, pwm_cnt => pwm_cnt, pwm => PWM); counter_1 : counter generic map ( WIDTH => 16, MAX => 2**16 - 2) port map ( clk => mclk, reset => puc, count => pwm_cnt); -------------------------------------------------------------------------------- per_dout <= uart_dout or omsp_quadcount_dout or omsp_pwm_dout; irq <= (6 => uart_irq, 7 => omsp_quadcount_irq, others => '0'); ROT_FEED <= '1'; end rtl;