This is a sample design for Virtex-II V2MB100 Development board using softcore
MCU openMSP430 <http://opencores.org/project,openmsp430>.


TOOLS USED:
================================================================================
  - Xilinx ISE 9.2 (not the WebPack edition!)
  - msp430-gcc 4.4.5


DESCRIPTION:
================================================================================
Sample shows how to use the openMSP430 softcore MCU and connected
periphery. These are rs-232 communication port, quadrature counter and PWM
generator.

For more detailed explanation of exact function see "software/main.c" file.

I/O description is in "openMSP430_uart.ucf" file.

On-board 24MHz oscillator is used (make sure it's not disabled!).

Parameters of rs-232 are 8N1 115200 baud.


BUILDING:
================================================================================
There is no *.ise project file, the whole process of building and
transfering of the design to the target FPGA is automated by using GNU
make. There are two Makefiles: "software/Makefile" and "build/Makefile".

The first one handles building of software for the MCU and need not be called
directly.

The second one is the main Makefile. (See it for more informations.)

Executing "cd build && make" should produce desired bitfile if an environment
is properly initialized.

If Xilinx ISE Impact is working with your JTAG adapter, then executing 
"cd build && make download" builds the design and transfers it to the target 
FPGA immediately.


PROJECT OVERVIEW:
================================================================================

  |-- build/                - building directory
  |   `-- Makefile          - main Makefile
  |
  |-- coregen/              - generated memory entities used by MCU
  |-- openmsp430/           - GIT submodule with MCU
  |-- quadcount/            - GIT submodule with quadrature counter
  |-- software/             - software for MCU
  |   |-- hardware.h        - description of MCU HW, periphery, ...
  |   |-- main.c            - sample application
  |   |-- Makefile
  |   |-- uart.c            - UART periphery routines
  |   `-- uart.h
  |-- uart/                 - GIT submodule with UART periphery
  |
  |-- counter.vhd           - Generic counter needed to generate PWM
  |-- memory.bmm            - Descripton of MCU memory map
  |-- omsp_pwm.vhd          - MCU PWM periphery
  |-- omsp_quadcount.vhd    - MCU interface to quadcount submodule
  |-- openMSP430_defines.v  - configuration of MCU (RAM & ROM size, mult, ...)
  |
  |-- openMSP430_uart.prj   - Description of VHDL and Verilog source files
  |-- openMSP430_uart.ucf   - Constraints files (pin positions, timing, ...)
  |
  |-- openMSP430_uart.vhd   - Top-level source file
  |
  `-- README