From 0e39c3079f3bd0c4f9ba6b71e9b2cc136d90d8a1 Mon Sep 17 00:00:00 2001 From: Vladimir Burian Date: Mon, 14 Feb 2011 20:24:15 +0100 Subject: [PATCH] Added top-module. Only reset, clock (24MHz) and rs-232 TXD, RXD signals are conected. --- build/Makefile | 2 +- top_plasma.prj | 5 +++++ top_plasma.ucf | 16 ++++++++++++++++ top_plasma.vhd | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+), 1 deletion(-) create mode 100644 top_plasma.ucf create mode 100644 top_plasma.vhd diff --git a/build/Makefile b/build/Makefile index 4ea07c7..401fe88 100644 --- a/build/Makefile +++ b/build/Makefile @@ -38,7 +38,7 @@ # Dependicies are handled, so in most cases only 'download' target is called. -TOP = +TOP = top_plasma DEVICE = xc2v1000-fg456 PRJ = ${TOP}.prj diff --git a/top_plasma.prj b/top_plasma.prj index 8cc550a..2debbda 100644 --- a/top_plasma.prj +++ b/top_plasma.prj @@ -18,3 +18,8 @@ vhdl work plasma/vhdl/shifter.vhd vhdl work plasma/vhdl/uart.vhd vhdl work plasma/vhdl/ram_xilinx.vhd vhdl work plasma/vhdl/plasma.vhd + +# Top module +#================================================== +vhdl work top_plasma.vhd + diff --git a/top_plasma.ucf b/top_plasma.ucf new file mode 100644 index 0000000..f33685d --- /dev/null +++ b/top_plasma.ucf @@ -0,0 +1,16 @@ +#==============================================================================# +# Clock & Reset # +#==============================================================================# + +NET "CLK_24MHz" LOC = "A11" | PERIOD = 41.7 ns LOW 20.9 ns; + +NET "RESET_N" LOC = "B6"; + + +#==============================================================================# +# RS-232 Port # +#==============================================================================# + +NET "TXD" LOC = "A7"; # output from the board (from FPGA) +NET "RXD" LOC = "B7"; # input to the board (to FPGA) + diff --git a/top_plasma.vhd b/top_plasma.vhd new file mode 100644 index 0000000..17dee5c --- /dev/null +++ b/top_plasma.vhd @@ -0,0 +1,51 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +entity top_plasma is + port ( + CLK_24MHz : in std_logic; + RESET_N : in std_logic; + RXD : in std_logic; + TXD : out std_logic); +end entity top_plasma; + +-------------------------------------------------------------------------------- + +architecture compose of top_plasma is + + signal clk : std_logic; + signal reset : std_logic; + +begin + + clk <= CLK_24MHz; + reset <= not RESET_N; + + + plasma_1: entity work.plasma + generic map ( + memory_type => "XILINX_16X", + log_file => "UNUSED", + ethernet => '0', + use_cache => '0') + port map ( + clk => clk, + reset => reset, + uart_write => TXD, + uart_read => RXD, + address => open, + byte_we => open, + data_write => open, + data_read => (others => '0'), + mem_pause_in => '0', + no_ddr_start => open, + no_ddr_stop => open, + gpio0_out => open, + gpioA_in => (others => '0')); + + +end architecture compose; + -- 2.39.2