rtime.felk.cvut.cz Git - fpga/virtex2/plasma.git/log

]> rtime.felk.cvut.cz Git - fpga/virtex2/plasma.git/log

Vladimir Burian [Tue, 15 Feb 2011 20:00:56 +0000 (21:00 +0100)]

Added software Makefile.

Design is now complete and test applications can be executed.

Vladimir Burian [Tue, 15 Feb 2011 19:56:24 +0000 (20:56 +0100)]

Added two Plasma MIPS test applications from original project.

Vladimir Burian [Tue, 15 Feb 2011 19:54:38 +0000 (20:54 +0100)]

Add map of Plasma MIPS RAMs.

"ram_xilinx.bmm" was created from "plasma/vhdl/ram_xilinx.bmm" template.

Vladimir Burian [Tue, 15 Feb 2011 19:51:30 +0000 (20:51 +0100)]

Main Makefile - bug fixed.

*.bmm now needs not be in the ${SRC} directory.

Vladimir Burian [Tue, 15 Feb 2011 19:46:24 +0000 (20:46 +0100)]

Correct baud-rate set.

Vladimir Burian [Tue, 15 Feb 2011 19:41:06 +0000 (20:41 +0100)]

Plasma MIPS submodule version changed.

Vladimir Burian [Mon, 14 Feb 2011 19:24:15 +0000 (20:24 +0100)]

Added top-module.

Only reset, clock (24MHz) and rs-232 TXD, RXD signals are conected.

Vladimir Burian [Mon, 14 Feb 2011 18:53:23 +0000 (19:53 +0100)]

Added build system and initial *.prj file.

Vladimir Burian [Mon, 14 Feb 2011 18:49:37 +0000 (19:49 +0100)]

Added Plasma "Lightweight" submodule.

This project is a test and example of Plasma MIPS "Lightweight"
in Virtex2 FPGA.

Plasma - most MIPS I - test top level design for Virtex 2 V2MB1000 board