#==============================================================================# # Clock & Reset # #==============================================================================# # RESET is low active! NET "CLK_24MHz" LOC = "A11" | PERIOD = 41.7 ns LOW 20.9 ns; NET "RESET" LOC = "B6"; #==============================================================================# # RS-232 Port # #==============================================================================# NET "TXD" LOC = "A7"; # output from the board (from FPGA) NET "RXD" LOC = "B7"; # input to the board (to FPGA) #==============================================================================# # LED outputs # #==============================================================================# # LEDs are connected to the ground NET "LED0" LOC = "E10"; # Display2<5> NET "LED1" LOC = "A8"; # Display2<1> NET "LED2" LOC = "E7"; # Display2<3> #==============================================================================# # LP_MPW1 BOARD # #==============================================================================# # This board with 3-phase power outputs and converters of hall and IRC # signals is connected to the J4 header (LVDS TRANSMIT). NET "PWM0" LOC = "F4" | IOSTANDARD = "LVCMOS33"; NET "PWM0_EN" LOC = "F3" | IOSTANDARD = "LVCMOS33"; NET "PWM1" LOC = "G4" | IOSTANDARD = "LVCMOS33"; NET "PWM1_EN" LOC = "G3" | IOSTANDARD = "LVCMOS33"; NET "PWM2" LOC = "H4" | IOSTANDARD = "LVCMOS33"; NET "PWM2_EN" LOC = "H3" | IOSTANDARD = "LVCMOS33"; NET "IRC_INDEX" LOC = "J4" | IOSTANDARD = "LVCMOS33"; NET "IRC_A" LOC = "J3" | IOSTANDARD = "LVCMOS33"; NET "IRC_B" LOC = "K4" | IOSTANDARD = "LVCMOS33"; NET "HAL0" LOC = "J5" | IOSTANDARD = "LVCMOS33"; NET "HAL1" LOC = "K5" | IOSTANDARD = "LVCMOS33"; NET "HAL2" LOC = "K6" | IOSTANDARD = "LVCMOS33";