library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;

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entity capture_reg16 is
  port (
    -- Peripheral bus interface
    ACK_O  : out std_logic;
    ADR_I  : in  std_logic_vector (0 downto 0);
    CLK_I  : in  std_logic;
    DAT_O  : out std_logic_vector (15 downto 0);
    SEL_I  : in  std_logic;
    STB_I  : in  std_logic;
    -- QCounter component interface
	EVENT_I   : in  std_logic;
    CAPTURE_I : in  std_logic_vector (31 downto 0));
end capture_reg16;

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architecture behavioral of capture_reg16 is
  
  signal CR_DAT_O : std_logic_vector (31 downto 0);

--------------------------------------------------------------------------------

begin

  with ADR_I select
    DAT_O <= 
    CR_DAT_O (15 downto  0) when "0",
    CR_DAT_O (31 downto 16) when "1",
    (others => 'X')         when others;


  capture_reg0 : entity work.capture_reg
    generic map (
      W => 32)
    port map (
   	  ACK_O  => ACK_O,
      CLK_I  => CLK_I,
      DAT_O  => CR_DAT_O,
      SEL_I  => SEL_I,
      STB_I  => STB_I,
      EVENT_I   => EVENT_I,
      CAPTURE_I => CAPTURE_I);

end behavioral;