From e75bfd1b2f384167b93256400ec034d0b6b906fe Mon Sep 17 00:00:00 2001
From: Vladimir Burian <buriavl2@fel.cvut.cz>
Date: Sat, 9 Apr 2011 21:11:27 +0200
Subject: [PATCH] Modified top-level makefile.

Now it is interconnected with Ocera-makefile system.
---
 build/Makefile | 28 ++++++++++++++++++++--------
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/build/Makefile b/build/Makefile
index 1ab626a..d9c720c 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -1,19 +1,25 @@
 # TOP           - Name of the top-level module
 # DEVICE        - Name of the FPGA device (device-package-speed)
 # PRJ           - Name of .prj file with names of all source files. See XST manual.
+# UCF           - Name of the user constraints file
 # BMM           - If design contains initialized memories, softcore MCU, etc., this
 #                 file describes mapping of .elf file to these memories. Only one
 #                 .bmm file can be used.
-# ELF           - File containing initialization data of memories described by
-#                 previously defined .bmm file. Format can be .elf or .mem.
-#                 When the file does not exist, make is called in ELF directory with
-#                 ELF file name as a target.
 # SEARCH_DIRS   - Directories to search when searching for netlists (.ngc, ...).
 #                 See NGDBUILD manual.
 # JTAG_POS      - Position of device in JTAG chain. Used when downloading bit stream.
 # INTSTYLE      - Style of screen output. (ise | xflow | silent)
 # SRC           - Path to the source directory. All other paths are relative to this.
 
+# Makefile is interconnected with Ocera-makefile system by the following properties
+# ARCH
+# BOARD
+# APP           - application name
+# SW_SRC        - directory name within $(SRC) dir where OC-makefile is called.
+#                 By default it's software/$(ARCH)-$(BOARD)-$(APP)
+# ELF           - File containing initialization data of memories described by
+#                 previously defined .bmm file. Format can be .elf or .mem.
+
 
 # Targets desctiption:
 #  - synthesize : Synthesize all VHDL and Verilog source files, libraries, etc.
@@ -44,8 +50,13 @@ DEVICE          = xc2v1000-fg456
 PRJ             = $(TOP).prj
 UCF             = $(TOP).ucf
 
+ARCH            = msp430
+BOARD           = virtex2
+APP             = cmdproc_test
+
 BMM             = memory.bmm
-ELF             = software/ta_uart.elf
+SW_SRC          = software/$(ARCH)-$(BOARD)-$(APP)
+ELF             = $(SW_SRC)/_compiled/bin/$(APP)
 
 SEARCH_DIRS     = 
 
@@ -57,7 +68,7 @@ SRC             = ..
 #===============================================================================
 # Abbreviations of frequently used file names.
 
-ifneq ($(strip $(ELF)),)
+ifneq ($(strip $(APP)),)
   BITFILE = $(TOP)_elf.bit
 else
   BITFILE = $(TOP).bit
@@ -124,7 +135,8 @@ $(TOP)_elf.bit: $(TOP).bit $(BMM_LOCAL_BD) $(SRC)/$(ELF)
 
 .PHONY: $(SRC)/$(ELF)
 $(SRC)/$(ELF):
-	make -C $(@D) $(@F)
+	make -C $(SRC)/$(SW_SRC)
+	ln -sf $(APP) $(SRC)/$(ELF).elf
 
 download: $(BITFILE) download-only
 download-only:
@@ -142,7 +154,7 @@ download-only:
 clean:
 	ls | grep -v ^Makefile$$ | xargs rm -rf
 	rm -f $(addprefix $(SRC)/,$(PRJ:.prj=.d))
-	make -C $(SRC)/$(dir $(ELF)) clean
+	make -C $(SRC)/$(SW_SRC) distclean
 
 #===============================================================================
 
-- 
2.39.2