+ Top level design

[fpga/virtex2/blink.git] / openMSP430_fpga.ucf

diff --git a/openMSP430_fpga.ucf b/openMSP430_fpga.ucf
new file mode 100644 (file)
index 0000000..7649e6c
--- /dev/null
+++ b/openMSP430_fpga.ucf
@@ -0,0 +1,31 @@
+#==============================================================================#
+# Clock & Reset                                                                #
+#==============================================================================#
+
+# V munualu jsou piny prohozeny!
+#NET "CLK_100MHz"        LOC = "B11" |     PERIOD =  10.0 ns LOW   5.0 ns;
+NET "CLK_24MHz"         LOC = "A11" |     PERIOD =  41.7 ns LOW  20.9 ns;
+
+NET "RESET"             LOC = "B6";
+
+
+#==============================================================================#
+# 7-Segment Display                                                            #
+#==============================================================================#
+
+NET "DISPLAY1<0>"       LOC = "D9";
+NET "DISPLAY1<1>"       LOC = "C9";
+NET "DISPLAY1<2>"       LOC = "F11";
+NET "DISPLAY1<3>"       LOC = "F9";
+NET "DISPLAY1<4>"       LOC = "F10";
+NET "DISPLAY1<5>"       LOC = "D10";
+NET "DISPLAY1<6>"       LOC = "C10";
+
+NET "DISPLAY2<0>"       LOC = "B9";
+NET "DISPLAY2<1>"       LOC = "A8";
+NET "DISPLAY2<2>"       LOC = "B8";
+NET "DISPLAY2<3>"       LOC = "E7";
+NET "DISPLAY2<4>"       LOC = "E8";
+NET "DISPLAY2<5>"       LOC = "E10";
+NET "DISPLAY2<6>"       LOC = "E9";
+