+ Top level design

[fpga/virtex2/blink.git] / openMSP430_fpga.prj

diff --git a/openMSP430_fpga.prj b/openMSP430_fpga.prj
new file mode 100644 (file)
index 0000000..58de78a
--- /dev/null
+++ b/openMSP430_fpga.prj
@@ -0,0 +1,26 @@
+verilog work openmsp430/omsp_alu.v
+verilog work openmsp430/omsp_clock_module.v
+verilog work openmsp430/omsp_dbg.v
+verilog work openmsp430/omsp_dbg_hwbrk.v
+verilog work openmsp430/omsp_dbg_uart.v
+verilog work openmsp430/omsp_execution_unit.v
+verilog work openmsp430/omsp_frontend.v
+verilog work openmsp430/omsp_mem_backbone.v
+verilog work openmsp430/omsp_multiplier.v
+verilog work openmsp430/omsp_register_file.v
+verilog work openmsp430/omsp_sfr.v
+verilog work openmsp430/omsp_watchdog.v
+verilog work openmsp430/openMSP430.v
+verilog work openmsp430/openMSP430_undefines.v
+verilog work openmsp430/timescale.v
+
+verilog work openMSP430_defines.v
+
+verilog work openmsp430/periph/omsp_gpio.v
+verilog work openmsp430/periph/omsp_timerA.v
+
+vhdl work coregen/ram_8x512.vhd
+vhdl work coregen/rom_8x2k.vhd
+
+vhdl work openMSP430_fpga.vhd
+