From: Vladimir Burian <buriavl2@fel.cvut.cz>
Date: Fri, 28 Jan 2011 20:30:50 +0000 (+0100)
Subject: Receiver control FSM prototype.
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/uart.git/commitdiff_plain/660aa732936779b9411182d719f5e38d9a81a3e8

Receiver control FSM prototype.
---

diff --git a/rx_control.vhd b/rx_control.vhd
new file mode 100644
index 0000000..ad10c6d
--- /dev/null
+++ b/rx_control.vhd
@@ -0,0 +1,101 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity rx_control is
+  port (
+    clk           : in  std_logic;
+    reset         : in  std_logic;
+    rx            : in  std_logic;
+    bad_start_bit : in  std_logic;
+    bad_stop_bit  : in  std_logic;
+    rx_ready      : in  std_logic;
+    rx_reset      : out std_logic;
+    rx_en         : out std_logic;
+    fifo_we       : out std_logic;
+    clk_en        : out std_logic);
+end entity rx_control;
+
+--------------------------------------------------------------------------------
+
+architecture behavioral of rx_control is
+
+  type state_t is (resetting, waiting, next_frame, receiving);
+
+  signal state : state_t;
+
+--------------------------------------------------------------------------------
+
+begin
+
+  process (clk, reset) is
+  begin
+    if reset = '1' then
+      state    <= waiting;
+      rx_reset <= '0';
+      rx_en    <= '0';
+      fifo_we  <= '0';
+      clk_en   <= '0';
+
+    elsif clk'event and clk = '1' then
+      case state is
+        when resetting =>
+          state    <= waiting;
+          rx_reset <= '0';
+          rx_en    <= '0';
+          fifo_we  <= '0';
+          clk_en   <= '0';
+
+
+        when waiting =>
+          rx_reset <= '0';
+          rx_en    <= '0';
+          fifo_we  <= '0';
+          clk_en   <= '0';
+
+          if rx = '0' then
+            state  <= next_frame;
+            rx_en  <= '1';
+            clk_en <= '1';
+          end if;
+
+
+        when next_frame =>
+          rx_reset <= '0';
+          rx_en    <= '1';
+          fifo_we  <= '0';
+          clk_en   <= '1';
+
+          if rx_ready = '0' then
+            if bad_start_bit = '1' then
+              state    <= resetting;
+              rx_reset <= '1';
+              rx_en    <= '0';
+              clk_en   <= '0';
+
+            else
+              state <= receiving;
+              rx_en <= '0';
+            end if;
+          end if;
+
+
+        when receiving =>
+          rx_reset <= '0';
+          rx_en    <= '0';
+          fifo_we  <= '0';
+          clk_en   <= '1';
+
+          if rx_ready = '1' then
+            state   <= waiting;
+            fifo_we <= '1';
+            clk_en  <= '0';
+          end if;
+
+      end case;
+    end if;
+  end process;
+
+end architecture behavioral;
+
diff --git a/tb/Makefile b/tb/Makefile
index 88f78a0..3f6333e 100644
--- a/tb/Makefile
+++ b/tb/Makefile
@@ -4,7 +4,8 @@ VHDL_ENTITIES = uart.o \
                 fifo.o \
                 baud_gen.o \
                 tx_control.o \
-                rx.o
+                rx.o \
+                rx_control.o
 
 STOP_TIME     = 50us