library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--------------------------------------------------------------------------------
-- Transmitter control FSM
--
-- Finite state machine controlling interconnection of FIFO buffer and output
-- shift register.
--------------------------------------------------------------------------------

entity tx_control is
  port (
    clk        : in  std_logic;
    reset      : in  std_logic;
    tx_ready   : in  std_logic;
    fifo_empty : in  std_logic;
    tx_we      : out std_logic;
    fifo_pop   : out std_logic
  );
end tx_control;

--------------------------------------------------------------------------------

architecture behavioral of tx_control is
  
  type state_t is (waiting, next_frame, transmitting);
  
  signal state : state_t := waiting;

--------------------------------------------------------------------------------

begin

  process (clk, reset)
  begin
    if (rising_edge(clk)) then
      if (reset = '1') then
        state <= waiting;

      else
        case state is
          when waiting =>
            if (fifo_empty = '0') then
              state <= next_frame;
            end if;
          
          when next_frame =>
            if (tx_ready = '0') then
              state <= transmitting;
            end if;
          
          when transmitting =>
            if (tx_ready = '1') then
              if (fifo_empty = '0') then
                state <= next_frame;
              else
                state <= waiting;
              end if;
            end if;
        end case;
      end if;
    end if;
  end process;


  process (state, tx_ready)
  begin
    case state is
      when waiting =>
        tx_we <= '0';
        fifo_pop <= '0';
        
      when next_frame =>
        tx_we <= '1';
        if (tx_ready = '0') then
          fifo_pop <= '1';
        else
          fifo_pop <= '0';
        end if;

      when transmitting =>
        tx_we <= '0';
        fifo_pop <= '0';
    end case;
  end process;

--------------------------------------------------------------------------------

end behavioral;