library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tb_fifo is
end tb_fifo;


architecture testbench of tb_fifo is

  component fifo is
    generic (
      width : integer := 2
    );
    port (
      clk      : in  std_logic;
      reset    : in  std_logic;
      we       : in  std_logic;
      re       : in  std_logic;
      d_in     : in  std_logic_vector (7 downto 0);
      d_out    : out std_logic_vector (7 downto 0);
      overflow : out std_logic
    );
  end component;
  
  signal clk   : std_logic;
  signal reset : std_logic;
  signal we       : std_logic;
  signal re       : std_logic;
  signal d_in     : std_logic_vector (7 downto 0) := (others => '0');
  signal d_out    : std_logic_vector (7 downto 0);
  signal length   : std_logic_vector (2 downto 0);
  signal overflow : std_logic;
  
  constant period : time := 1 us;
  constant offset : time := 2 us;
  
begin
  UUT : fifo port map (
    clk      => clk,
    reset    => reset,
    we       => we,
    re       => re,
    d_in     => d_in,
    d_out    => d_out,
    overflow => overflow
  );

  process
  begin
    clk <= '0';
    wait for offset;
    
    loop
      clk <= '1';
      wait for period/2;
      clk <= '0';
      wait for period/2;
    end loop;
  end process;


  process
  begin
    reset <= '0';
    wait for period;
    reset <= '1';
    wait for period;
    reset <= '0';
    wait;
  end process;


  process
  begin
    we <= '0';
    re <= '0';
    d_in <= "00000000";
    
    wait for 0.1 * period;

    wait for 2 * period;
    d_in <= "01000001";
    we <= '1';
    
    wait for period;
    d_in <= "01000010";
    
    wait for period;
    d_in <= "01000011";
    
    wait for period;
    d_in <= "01000011";
    
    wait for period;
    d_in <= "01000101";
    
    wait for period;
    we <= '0';
    
    wait for 2 * period;
    re <= '1';
    
    wait for period;
    re <= '0';
    
    wait;
  end process;
  
end testbench;