library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tb_baud_gen is
end tb_baud_gen;


architecture testbench of tb_baud_gen is

  component baud_gen is
    port (
      clk      : in  std_logic;
      ce       : in  std_logic;
      reset    : in  std_logic;
      scale    : in  std_logic_vector (15 downto 0);
      clk_baud : out std_logic
    );
  end component;
  
  signal clk   : std_logic;
  signal ce    : std_logic;
  signal reset : std_logic;
  
  constant period : time := 2 us;
  constant offset : time := 2 us;
  
  signal scale    : std_logic_vector (15 downto 0);
  signal clk_baud : std_logic;

--------------------------------------------------------------------------------
  
begin
  UUT : baud_gen port map (
    clk      => clk,
    ce       => ce,
    reset    => reset,
    scale    => scale,
    clk_baud => clk_baud
  );

  process
  begin
    clk <= '0';
    wait for offset;
    
    loop
      clk <= '1';
      wait for period/2;
      clk <= '0';
      wait for period/2;
    end loop;
  end process;


  process
  begin
    reset <= '0';
    ce    <= '0';
    
    wait for 1.2 * period;
    reset <= '1';
    wait for 3 * period;
    reset <= '0';

    wait for 2 * period;
    ce <= '1';
    wait for 7 * period;
    ce <= '0';

    wait;
  end process;


  process
  begin
    scale <= X"0000";
  
    wait until reset = '0' and clk = '1';
    wait for 0.1 * period;
    
    wait;
  end process;
  
end testbench;