- component div_20 is
- port (
- clk : in std_logic;
- clk_2k : out std_logic);
- end component;
-
- component hex2lcd is
- port (
- hex : in std_logic_vector (3 downto 0);
- lcd : out std_logic_vector (6 downto 0));
- end component;
-
- component lcd_mux is
- port (
- clk : in std_logic;
- cnt : in std_logic;
- data_in : in std_logic_vector (6 downto 0);
- lcd_seg : out std_logic_vector (6 downto 0);
- lcd_com : out std_logic;
- lcd_dp : out std_logic);
- end component;
-
- component qcounter is
- port (
- clock : in std_logic;
- reset : in std_logic;
- a0, b0 : in std_logic;
- qcount : out std_logic_vector (31 downto 0);
- a_rise : out std_logic;
- a_fall : out std_logic;
- b_rise : out std_logic;
- b_fall : out std_logic;
- ab_event : out std_logic;
- ab_error : out std_logic);
- end component;
-
-