library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

--------------------------------------------------------------------------------
-- This module controls the bias reversal for a single 7-segment display. The
-- clk input xor's the segment data to cause the segment biasing to be swapped.
-- The cnt signal should be about 20-30 Hz for LCD to function correctly. The
-- common signal is also bias reversed at this same frequency.
--
-- Example: A is off and B is on, COM is driven by clk signal.
--         __    __    __    __ 
--   A  __|  |__|  |__|  |__|  |__
--      __    __    __    __    __
--   B    |__|  |__|  |__|  |__|  
--         __    __    __    __ 
-- COM  __|  |__|  |__|  |__|  |__
--
--------------------------------------------------------------------------------

entity lcd_mux is
  port (
    clk     : in  std_logic;
    cnt     : in  std_logic;
    data_in : in  std_logic_vector (6 downto 0);
    lcd_seg : out std_logic_vector (6 downto 0);
    lcd_com : out std_logic;
    lcd_dp  : out std_logic);
end lcd_mux;

--------------------------------------------------------------------------------

architecture behavioral of lcd_mux is
begin
  
  process (clk)
  begin
    if (clk'event and clk = '1') then
      lcd_seg(0) <= data_in(0) xor cnt;
      lcd_seg(1) <= data_in(1) xor cnt;
      lcd_seg(2) <= data_in(2) xor cnt;
      lcd_seg(3) <= data_in(3) xor cnt;
      lcd_seg(4) <= data_in(4) xor cnt;
      lcd_seg(5) <= data_in(5) xor cnt;
      lcd_seg(6) <= data_in(6) xor cnt;
      lcd_com    <= cnt;
      lcd_dp     <= '0' xor cnt;
    end if;
  end process;
  
end Behavioral;