library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

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-- This module divides the incoming clock by 2^20 and outputs the 20th bit of
-- the counter as clk_2k.
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entity div_20 is
  port (
    clk    : in  std_logic;
    clk_2k : out std_logic);
end div_20;

--------------------------------------------------------------------------------

architecture Behavioral of div_20 is
  
  signal count : std_logic_vector (19 downto 0);
  
begin
  
  process(clk)
  begin
    if(clk'event and clk = '1') then
      count <= count + "00000000000000000001";
    end if;
  end process;

  clk_2k <= count(19);
  
end Behavioral;