From d2356c3c1fdf6e7004675f205ddefc3385efad8f Mon Sep 17 00:00:00 2001 From: Martin Prudek Date: Fri, 27 Mar 2015 11:19:56 +0100 Subject: [PATCH] zmena hodin pro spi z SCLK (500kHz) na GPCLK (2,4MHZ). Pomoci GPCLK je nyni 'vzorkovano', zda doslo ke zmene logicke hodnoty na SCLK. Takto je detekovana nabezna a sestupna hrana. Zakladni funkcnost overena na 'spi repeateru'. Pretrvavaji problemy s kodovanim (endianita & prazdny posuvny registr na zacatku prenosu..?). --- pmsm-control/rpi_mc_simple_dc.vhdl | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl index d3f69bc..7b4ef78 100644 --- a/pmsm-control/rpi_mc_simple_dc.vhdl +++ b/pmsm-control/rpi_mc_simple_dc.vhdl @@ -20,7 +20,7 @@ entity rpi_mc_simple_dc is port ( gpio2: in std_logic; -- SDA gpio3: in std_logic; -- SCL - gpio4: out std_logic; -- CLK + gpio4: in std_logic; -- CLK gpio14: in std_logic; -- Tx gpio15: in std_logic; -- Rx gpio17: out std_logic; -- RTS @@ -103,8 +103,10 @@ architecture behavioral of rpi_mc_simple_dc is port (A: in std_logic; Y: out std_logic); end component; + signal spiclk_old_lvl: std_logic :='0'; --pro detekci hrany SPI hodin signal pwm_in, pwm_dir_in: std_logic; signal spi_clk: std_logic; + signal gpio_clk: std_logic; signal dat_reg : STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); --registr pro SPI -- attribute syn_noprune of gpio2 : signal is true; @@ -114,11 +116,21 @@ architecture behavioral of rpi_mc_simple_dc is begin -- PLL as a reset generator + + --zesileni signalu hodin SPI - bez zesileni nelze syntetizovat copyclk: CLKINT port map ( a => gpio11, y => spi_clk ); + + --zesileni signalu GPIO CLK + copyclk2: CLKINT + port map ( + a => gpio4, + y => gpio_clk + ); + -- pll: pll50to200 -- port map ( -- powerdown => '1', @@ -130,7 +142,7 @@ begin -- upon power-on -- clock <= clkm; - dummy_unused <= gpio2 and gpio3 and + dummy_unused <= gpio2 and gpio3 and gpio4 and gpio5 and gpio6 and gpio12 and gpio13 and gpio14 and gpio15 and gpio16 and gpio19 and @@ -163,20 +175,21 @@ begin - process (spi_clk) --nufunguje preo piny 11,17,27 funguje pro 4,18,22,ext_sclk,10 + process (gpio_clk) begin --if (gpio11'event and gpio11 = '1') then -- rising edge of SCK - if (rising_edge(spi_clk)) then + if ((spi_clk = '1') and (spiclk_old_lvl = '0') ) then if (gpio7 = '0') then -- SPI CS must be selected -- shift serial data into dat_reg on each rising edge -- of SCK, MSB first dat_reg(7 downto 0) <= dat_reg(6 downto 0) & gpio10; - + spiclk_old_lvl <= '1'; end if; - elsif (falling_edge(spi_clk)) then + elsif ((spi_clk = '0') and (spiclk_old_lvl = '1')) then if (gpio7 = '0') then gpio9 <= dat_reg(7); --zapisujeme nejdriv MSB + spiclk_old_lvl <= '0'; end if; end if; end process; -- 2.39.2