From 5fa52f26f4baf2968a7f611a354854db5766ab24 Mon Sep 17 00:00:00 2001 From: Martin Prudek Date: Mon, 6 Apr 2015 16:20:56 +0200 Subject: [PATCH] Tested version of ADC. --- pmsm-control/rpi_mc_simple_dc.vhdl | 101 +++++++++++++++++++---------- 1 file changed, 65 insertions(+), 36 deletions(-) diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl index 0ff098e..7b09532 100644 --- a/pmsm-control/rpi_mc_simple_dc.vhdl +++ b/pmsm-control/rpi_mc_simple_dc.vhdl @@ -113,7 +113,7 @@ architecture behavioral of rpi_mc_simple_dc is ); end component; - type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,reset); + type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,f15,r15,reset,rst_wait); signal state : state_type; type channel_type is (ch0, ch1, ch2); @@ -247,33 +247,58 @@ begin process variable data_ready : std_logic; variable channel: channel_type; + variable reset_re: std_logic:='0'; + variable reset_count: integer:=0; begin wait until (gpio_clk'event and gpio_clk='1'); + + --reset rising edge detection + adc_rst_old(0)<=adc_reset; + adc_rst_old(1)<=adc_rst_old(0); + + if (adc_rst_old="01") then + reset_re:='1'; + end if; + case state is when reset=> - adc_scs<='1'; --active-high SS - data_ready:='0'; + reset_re:='0'; --clear reset flag + adc_scs<='1'; --active-low SS + adc_sclk<='0'; --lower clock + data_ready:='0'; --addresse are CH(A2,A1,A0): CH0:(0,0,1),CH1:(1,0,1),CH2:(0,1,0) adc_address<="001101010"; channel:=ch0; - when f1=> - adc_scs<='0'; --active-high SS + adc_channels(35 downto 0)<=(others=>'1'); --for debug only - remove this line! + adc_data(11 downto 0)<=(others=>'1'); + reset_count:=0; + state<=rst_wait; + when rst_wait=> + if (reset_count<10) then + reset_count:=reset_count+1; + if (reset_count=7) then + adc_scs<='0'; --give the adc some time to prepare before trensfer + end if; + else + state<=f1; + end if; + when f1=> --1st 'fallin edge' - its not falling edge in any case-if rst clock is low before adc_sclk<='0'; --clk adc_mosi<='1'; --start bit state<=r1; --next state - when r1=> --rising edge - adc_sclk<='1'; + when r1=> --1st rising edge (adc gets the start bit, we get date..) + adc_sclk<='1'; adc_data(5)<=adc_miso; state<=f2; when f2=> --2nd falling edge adc_sclk<='0'; adc_mosi<=adc_address(8); --A2 address state<=r2; - when r2=> --rising edge + when r2=> --2nd rising edge (adc gets A2 address) adc_sclk<='1'; adc_data(4)<=adc_miso; state<=f3; - when f3=> --3rd falling edge + when f3=> --3rd falling edge adc_sclk<='0'; adc_mosi<=adc_address(7); --A1 address state<=r3; @@ -285,7 +310,7 @@ begin adc_sclk<='0'; adc_mosi<=adc_address(6); --A0 address --shift the addresses - adc_address(8 downto 0)<=adc_address(5 downto 0) & adc_address(8 downto 6); + adc_address(8 downto 0)<=adc_address(5 downto 0) & adc_address(8 downto 6); state<=r4; when r4=> --rising edge adc_sclk<='1'; @@ -303,7 +328,7 @@ begin adc_sclk<='0'; adc_mosi<='1'; --SGL/DIF (HIGH - SGL=Single Ended) state<=r6; - when r6=> --rising edge + when r6=> --6th rising edge (we read last bit of conversion, adc gets SGL/DIF) adc_sclk<='1'; adc_data(0)<=adc_miso; state<=f7; @@ -311,21 +336,21 @@ begin adc_sclk<='0'; adc_mosi<='0'; --PD1 (power down - PD1=PD0=0 -> power down between conversion) state<=r7; - when r7=> --rising edge, data ready + when r7=> --7th rising edge, data ready adc_sclk<='1'; if (data_ready='1') then case channel is when ch0=> - --adc_channels(35 downto 24)<=adc_data(11 downto 0); - adc_channels(35 downto 24)<=(others=>'0'); + adc_channels(35 downto 24)<=adc_data(11 downto 0); + --adc_channels(35 downto 24)<=(others=>'0'); channel:=ch1; when ch1=> - --adc_channels(23 downto 12)<=adc_data(11 downto 0); - adc_channels(23 downto 12)<=(others=>'1'); + adc_channels(23 downto 12)<=adc_data(11 downto 0); + --adc_channels(23 downto 12)<=(others=>'1'); channel:=ch2; when ch2=> - --adc_channels(11 downto 0)<=adc_data(11 downto 0); - adc_channels(11 downto 0)<=(others=>'0'); + adc_channels(11 downto 0)<=adc_data(11 downto 0); + --adc_channels(11 downto 0)<=(others=>'0'); channel:=ch0; end case; end if; @@ -335,54 +360,58 @@ begin adc_sclk<='0'; adc_mosi<='0'; --PD0 state<=r8; - when r8=> --rising edge + when r8=> --8th rising edge (adc gets PD0) adc_sclk<='1'; state<=f9; - when f9=> --busy state between conversion, 9th falling edge + when f9=> --9th falling edge busy state between conversion (we write nothing) adc_sclk<='0'; state<=r9; - when r9=> --10th rising edge + when r9=> --9th rising edge (we nor ads get nothing) adc_sclk<='1'; - adc_data(11)<=adc_miso; state<=f10; - when f10=> + when f10=> --10th falling edge adc_sclk<='0'; state<=r10; - when r10=> --11th rising edge + when r10=> --10th rising edge (we read 1. bit of conversion) adc_sclk<='1'; - adc_data(10)<=adc_miso; + adc_data(11)<=adc_miso; state<=f11; when f11=> adc_sclk<='0'; state<=r11; - when r11=> --12th rising edge + when r11=> --11th rising edge adc_sclk<='1'; - adc_data(9)<=adc_miso; + adc_data(10)<=adc_miso; state<=f12; when f12=> adc_sclk<='0'; state<=r12; - when r12=> --13th rising edge + when r12=> --12th rising edge adc_sclk<='1'; - adc_data(8)<=adc_miso; + adc_data(9)<=adc_miso; state<=f13; when f13=> adc_sclk<='0'; state<=r13; - when r13=> --14th rising edge + when r13=> --13th rising edge adc_sclk<='1'; - adc_data(7)<=adc_miso; + adc_data(8)<=adc_miso; state<=f14; when f14=> adc_sclk<='0'; - --for rising edge detection in next cycle - adc_rst_old(0)<=adc_reset; - adc_rst_old(1)<=adc_rst_old(0); state<=r14; - when r14=> --15th rising edge + when r14=> --14th rising edge + adc_sclk<='1'; + adc_data(7)<=adc_miso; + state<=f15; + when f15=> + adc_sclk<='0'; + --for rising edge detection in next cycle + state<=r15; + when r15=> --15th rising edge adc_sclk<='1'; adc_data(6)<=adc_miso; - if (adc_rst_old="01") then --we check rising edge of reset + if (reset_re='1') then --we check rising edge of reset state<=reset; else state<=f1; -- 2.39.2