From 34de8485a125ab8edae50d0f1406462a82b56391 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Fri, 1 May 2015 17:02:07 +0200 Subject: [PATCH] Include SDC Synopsys Design Constraints file to the design file lists. This file allows fine definition of clocks relations and parameters. Signed-off-by: Pavel Pisa --- pmsm-control/syn.tcl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/pmsm-control/syn.tcl b/pmsm-control/syn.tcl index 19ab95a..b444b9d 100644 --- a/pmsm-control/syn.tcl +++ b/pmsm-control/syn.tcl @@ -3,7 +3,7 @@ project -new rpi_pmsm_control impl -name syn0 -#add_file pll50to200.vhd +add_file pll50to200.vhd add_file util.vhdl add_file qcounter.vhdl add_file dff.vhdl @@ -13,14 +13,14 @@ add_file adc_reader.vhdl # top-level add_file rpi_pmsm_control.vhdl -#add_file rpi_mc_simple_dc.sdc +add_file rpi_pmsm_control.sdc set_option -technology IGLOO set_option -part AGL250V5 set_option -package VQFP100 set_option -speed_grade std -set_option -frequency 40.0 +set_option -frequency 50.0 project -run project -save -- 2.39.2