From 203c29ad05f5650a142e7f77bc9d4b37c0e2d3d5 Mon Sep 17 00:00:00 2001 From: Martin Prudek Date: Sun, 5 Apr 2015 16:11:00 +0200 Subject: [PATCH] ADC state machine upgraded (reset added), ready for testing. --- pmsm-control/rpi_mc_simple_dc.vhdl | 54 +++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 9 deletions(-) diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl index 35de1b8..56401e5 100644 --- a/pmsm-control/rpi_mc_simple_dc.vhdl +++ b/pmsm-control/rpi_mc_simple_dc.vhdl @@ -113,9 +113,13 @@ architecture behavioral of rpi_mc_simple_dc is ); end component; - type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,f15,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15); + type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,reset); signal state : state_type; signal adc_data: std_logic_vector(11 downto 0); --ADC income data + signal adc_reset : std_logic; + signal adc_rst_old : std_logic_vector(1 downto 0); + signal adc_address: std_logic_vector(8 downto 0); + signal adc_channels: std_logic_vector(35 downto 0); signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin signal pwm_in, pwm_dir_in: std_logic; @@ -226,21 +230,30 @@ begin --sestupna hrana SS, pripravime data pro prenos - if ((ce0_old = "10") ) then + if (ce0_old = "10" ) then dat_reg(95 downto 64) <= position(31 downto 0); --pozice dat_reg(63 downto 61) <= hal_in(1 to 3); --halovy sondy - dat_reg(60 downto 0) <= (others => '1'); --zbytek zatim nuly - + dat_reg(60 downto 36) <= (others => '1'); --let the rest fill with ones + dat_reg(35 downto 0) <= adc_channels(35 downto 0); --current mesurments + elsif (ce0_old = "01") then --rising edge of SS, we should read the data + adc_reset<=dat_reg(95); end if; end process; process + variable data_ready : std_logic; + variable channel: std_logic_vector(1 downto 0); begin wait until (gpio_clk'event and gpio_clk='1'); case state is + when reset=> + adc_scs<='0'; --active-high SS + data_ready:='0'; + --addresse are CH(A2,A1,A0): CH0:(0,0,1),CH1:(1,0,1),CH2:(0,1,0) + adc_address<="001101010"; + channel:="00"; when f1=> adc_sclk<='0'; --clk - adc_scs<='0'; --active-high SS adc_mosi<='1'; --start bit state<=r1; --next state when r1=> --rising edge @@ -249,7 +262,7 @@ begin state<=f2; when f2=> --2nd falling edge adc_sclk<='0'; - adc_mosi<='0'; --A2 address + adc_mosi<=adc_address(8); --A2 address state<=r2; when r2=> --rising edge adc_sclk<='1'; @@ -257,7 +270,7 @@ begin state<=f3; when f3=> --3rd falling edge adc_sclk<='0'; - adc_mosi<='0'; --A1 address + adc_mosi<=adc_address(7); --A1 address state<=r3; when r3=> --rising edge adc_sclk<='1'; @@ -265,7 +278,9 @@ begin state<=f4; when f4=> --4th falling edge adc_sclk<='0'; - adc_mosi<='1'; --A0 address + adc_mosi<=adc_address(6); --A0 address + --shift the addresses + adc_address(8 downto 0)<=adc_address(5 downto 0) & adc_address(8 downto 6); state<=r4; when r4=> --rising edge adc_sclk<='1'; @@ -293,6 +308,20 @@ begin state<=r7; when r7=> --rising edge, data ready adc_sclk<='1'; + if (data_ready='1') then + case channel is + when "00"=> + adc_channels(35 downto 24)<=adc_data(11 downto 0); + channel:="01"; + when "01"=> + adc_channels(23 downto 12)<=adc_data(11 downto 0); + channel:="10"; + when "10"=> + adc_channels(11 downto 0)<=adc_data(11 downto 0); + channel:="00"; + end case; + end if; + data_ready:='1'; state<=f8; when f8=> --8th falling edge adc_sclk<='0'; @@ -340,8 +369,15 @@ begin adc_sclk<='0'; state<=r14; when r14=> --15th rising edge + adc_sclk<='1'; adc_data(6)<=adc_miso; - state<=f1; + adc_rst_old(0)<=adc_reset; + adc_rst_old(1)<=adc_rst_old(0); + if (adc_rst_old="01") then --we check rising edge of reset + state<=reset; + else + state<=f1; + end if; end case; end process; -- 2.39.2