fpga/rpi-motor-control.git
4 years agoChanged frequency to test,
Martin Prudek [Thu, 7 May 2015 14:44:39 +0000 (16:44 +0200)]
Changed frequency to test,

4 years agoBug fix: unconsistent changes of match signal caused twitches im motor movement....
Martin Prudek [Thu, 7 May 2015 12:41:05 +0000 (14:41 +0200)]
Bug fix: unconsistent changes of match signal caused twitches im motor movement. The match signal is now changed only at the end ow pwm cycle.

4 years agoChanged positions of PWM duty cycle bits in SPI communication.
Martin Prudek [Thu, 7 May 2015 10:34:58 +0000 (12:34 +0200)]
Changed positions of PWM duty cycle bits in SPI communication.

4 years agoRemoved duplicate signal adc_reset.
Martin Prudek [Sun, 3 May 2015 10:34:19 +0000 (12:34 +0200)]
Removed duplicate signal adc_reset.

4 years agoAdded synchronous detection o divided clk signal to adc_reader component.
Martin Prudek [Sun, 3 May 2015 10:21:09 +0000 (12:21 +0200)]
Added synchronous detection o divided clk signal to adc_reader component.

4 years agoBug fix: Added data propagation to MISO on falling edge of SE signal.
Martin Prudek [Sat, 2 May 2015 11:52:16 +0000 (13:52 +0200)]
Bug fix: Added data propagation to MISO on falling edge of SE signal.

4 years agoCorrect RPi-MI-1 board name to match PCB text.
Pavel Pisa [Fri, 1 May 2015 22:49:42 +0000 (00:49 +0200)]
Correct RPi-MI-1 board name to match PCB text.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
4 years agoChange license to LGPL and GPLv3+ options, fill authors according their real work...
Pavel Pisa [Fri, 1 May 2015 17:01:36 +0000 (19:01 +0200)]
Change license to LGPL and GPLv3+ options, fill authors according their real work on the project.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
4 years agoPMSM design: use signals with descriptive names for pins connected to RPi SPI.
Pavel Pisa [Fri, 1 May 2015 16:12:28 +0000 (18:12 +0200)]
PMSM design: use signals with descriptive names for pins connected to RPi SPI.

Remove these pins from global dummy signal expression which is used to
suppress error for nonexistent/eliminated design signals referrenced by PDC.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
4 years agoChange IRC recognition logic synchronous with main design clock.
Pavel Pisa [Fri, 1 May 2015 15:48:28 +0000 (17:48 +0200)]
Change IRC recognition logic synchronous with main design clock.

Use of external, not synchronized signal event as
the trigger condition results in creation of additional
clock domain which can result in all kinds of hazard
conditions when used to manipulate with else synchronous
design state.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
4 years agoInclude SDC Synopsys Design Constraints file to the design file lists.
Pavel Pisa [Fri, 1 May 2015 15:02:07 +0000 (17:02 +0200)]
Include SDC Synopsys Design Constraints file to the design file lists.

This file allows fine definition of clocks relations and parameters.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
4 years agoInclude in PMSM design to implement safe behavior when external clocks are not present.
Pavel Pisa [Fri, 1 May 2015 14:59:49 +0000 (16:59 +0200)]
Include in PMSM design to implement safe behavior when external clocks are not present.

The PLL is configured to synthesize 200 MHz clock from 50 MHz input.
The clock monitor holds PWM outputs low if the external clocks are
not present. The reference lost is recognized 6 in 8 cycles
of 200 MHz synthesized clock as well.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
4 years agoRename PMSM control design top level component to match VHDL file name and function.
Pavel Pisa [Fri, 1 May 2015 14:53:31 +0000 (16:53 +0200)]
Rename PMSM control design top level component to match VHDL file name and function.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
4 years agoModified ADC clk frequency from 3.2 MHz to 2.08Mhz
Martin Prudek [Thu, 30 Apr 2015 16:42:12 +0000 (18:42 +0200)]
Modified ADC clk frequency from 3.2 MHz to 2.08Mhz

4 years agoComplete commutation keeping vector of stator magnetic field perpendicular to vector...
Martin Prudek [Sun, 26 Apr 2015 19:36:26 +0000 (21:36 +0200)]
Complete commutation keeping vector of stator magnetic field perpendicular to vector of rotor magnetic field.

4 years agoSimple IRC position commutator added. And Very simple PID reg. added.
Martin Prudek [Sat, 18 Apr 2015 18:27:21 +0000 (20:27 +0200)]
Simple IRC position commutator added. And Very simple PID reg. added.

4 years agoState variables moved to new structure 'rpi_state'. Added semaphore to controll acces...
Martin Prudek [Sat, 18 Apr 2015 16:52:09 +0000 (18:52 +0200)]
State variables moved to new structure 'rpi_state'. Added semaphore to controll access to them. Also added computation of distance to index position.

4 years agoAdded counter-clockwise simple hall comutator.
Martin Prudek [Sat, 18 Apr 2015 13:30:27 +0000 (15:30 +0200)]
Added counter-clockwise simple hall comutator.

4 years agoAdded simple commutator.
Martin Prudek [Thu, 16 Apr 2015 19:35:51 +0000 (21:35 +0200)]
Added simple commutator.

4 years agoAdded reading of irc_index position.
Martin Prudek [Thu, 16 Apr 2015 17:25:43 +0000 (19:25 +0200)]
Added reading of irc_index position.

4 years agoAttemp to solve bug. ADC channels association should be pwm1-ch0 pwm2-ch1 pwm3-ch2...
Martin Prudek [Thu, 16 Apr 2015 14:02:32 +0000 (16:02 +0200)]
Attemp to solve bug. ADC channels association should be pwm1-ch0 pwm2-ch1 pwm3-ch2 (according to schema). In fact it is pwm1-ch1 pwm2-ch2 pwm3-ch0. Cant find the mistake.

4 years agoSending unique measured current value was replaced by current accumulator. Now multip...
Martin Prudek [Thu, 16 Apr 2015 09:59:39 +0000 (11:59 +0200)]
Sending unique measured current value was replaced by current accumulator. Now multiple summarised values are sent alongside with its count.

4 years agoCurrent measurment bits transferring via SPI from FPGA to RPi extended from 12 to...
Martin Prudek [Wed, 15 Apr 2015 19:04:19 +0000 (21:04 +0200)]
Current measurment bits transferring via SPI from FPGA to RPi extended from 12 to 24 bits. This is preparation for transferring sum of currents.

4 years agoBit positioning description changed after switching to 128-bit SPI.
Martin Prudek [Wed, 15 Apr 2015 18:31:58 +0000 (20:31 +0200)]
Bit positioning description changed after switching to 128-bit SPI.

4 years agoAdded testing SW in folder test_sw.
Martin Prudek [Wed, 15 Apr 2015 17:25:08 +0000 (19:25 +0200)]
Added testing SW in folder test_sw.

4 years agoFPGA<->RPiSPI data frame extended from 96bits to 128bits
Martin Prudek [Wed, 15 Apr 2015 14:59:51 +0000 (16:59 +0200)]
FPGA<->RPiSPI data frame extended from 96bits to 128bits

4 years agoProject renamed 'to rpi_pmsm_control'.
Martin Prudek [Wed, 15 Apr 2015 13:46:14 +0000 (15:46 +0200)]
Project renamed 'to rpi_pmsm_control'.

4 years agoAdded ADC reset after each FPGA<->RPi transfer. ADC channels manipulation improved.
Martin Prudek [Sun, 12 Apr 2015 13:21:41 +0000 (15:21 +0200)]
Added ADC reset after each FPGA<->RPi transfer. ADC channels manipulation improved.

4 years agoTransfer of PWM match data verified. Added back transmission of PWM match for debug...
Martin Prudek [Sun, 12 Apr 2015 11:29:11 +0000 (13:29 +0200)]
Transfer of PWM match data verified. Added back transmission of PWM match for debug purposses.

4 years agoADC reader moved to separate file.
Martin Prudek [Sat, 11 Apr 2015 09:46:32 +0000 (11:46 +0200)]
ADC reader moved to separate file.

4 years agoDisconnect PWM generators for debug purpose.
Martin Prudek [Sat, 11 Apr 2015 09:17:06 +0000 (11:17 +0200)]
Disconnect PWM generators for debug purpose.

4 years agoGPCLK frequency from RPi increased from 2Mhz to 50Mhz. To keep clk frequency for...
Martin Prudek [Sat, 11 Apr 2015 09:14:13 +0000 (11:14 +0200)]
GPCLK frequency from RPi increased from 2Mhz to 50Mhz. To keep clk frequency for ADC lower then 3.2Mhz, freqency divider(divides by 8) have been added.

4 years agoIntegration of mcpwm into toplevel entity.
Martin Prudek [Fri, 10 Apr 2015 09:57:54 +0000 (11:57 +0200)]
Integration of mcpwm into toplevel entity.

4 years agoPWM entity file added.
Martin Prudek [Thu, 9 Apr 2015 17:57:20 +0000 (19:57 +0200)]
PWM entity file added.

4 years agoTested version of ADC.
Martin Prudek [Mon, 6 Apr 2015 14:20:56 +0000 (16:20 +0200)]
Tested version of ADC.

4 years agoTested version of ADC state machine. Tested only to prove that 'something works'...
Martin Prudek [Sun, 5 Apr 2015 15:27:53 +0000 (17:27 +0200)]
Tested version of ADC state machine. Tested only to prove that 'something works'. Cannot verify measured data - so thah implemented communication protocol might not be workung.

4 years agoLittle changes to get rid of warnings.
Martin Prudek [Sun, 5 Apr 2015 14:54:53 +0000 (16:54 +0200)]
Little changes to get rid of warnings.

4 years agoADC state machine upgraded (reset added), ready for testing.
Martin Prudek [Sun, 5 Apr 2015 14:11:00 +0000 (16:11 +0200)]
ADC state machine upgraded (reset added), ready for testing.

4 years agoADC basic state machine. Not complete.
Martin Prudek [Sun, 5 Apr 2015 13:10:33 +0000 (15:10 +0200)]
ADC basic state machine. Not complete.

4 years agoSPI trigger changed to rising edge (formely falling)
Martin Prudek [Sun, 5 Apr 2015 11:39:36 +0000 (13:39 +0200)]
SPI trigger changed to rising edge (formely falling)

4 years agoHall sensors output added to spi frame.
Martin Prudek [Sat, 4 Apr 2015 17:21:32 +0000 (19:21 +0200)]
Hall sensors output added to spi frame.

4 years agoUnused CLKINT for SCLK removed.
Martin Prudek [Sat, 4 Apr 2015 16:55:12 +0000 (18:55 +0200)]
Unused CLKINT for SCLK removed.

4 years agoUnused lines removed.
Martin Prudek [Sat, 4 Apr 2015 16:47:22 +0000 (18:47 +0200)]
Unused lines removed.

4 years agoSpi upgrade. Previous solution didnt catch all the rising edges of SS.
Martin Prudek [Sat, 4 Apr 2015 16:43:29 +0000 (18:43 +0200)]
Spi upgrade. Previous solution didnt catch all the rising edges of SS.

4 years agoqcounter.vhdl and dff.vhdl added to syn.tcl
Martin Prudek [Sun, 29 Mar 2015 19:00:14 +0000 (21:00 +0200)]
qcounter.vhdl and dff.vhdl added to syn.tcl

4 years agopriprava na odesilani pozicez qcounteru - nelze synthetizovat
Martin Prudek [Sat, 28 Mar 2015 14:17:22 +0000 (15:17 +0100)]
priprava na odesilani pozicez qcounteru - nelze synthetizovat

4 years agozjednoduseni vzorkovani spi hodin gpio hodinami. Otestovano a funkcni. (SCLK 500...
Martin Prudek [Sat, 28 Mar 2015 12:12:22 +0000 (13:12 +0100)]
zjednoduseni vzorkovani spi hodin gpio hodinami. Otestovano a funkcni. (SCLK 500 KHz, GPCLK 2MHz)

4 years agoPredchozi reseni pouziti rychlejsich hodin pro vzorkovani pomalejsich hodin spi bylo...
Martin Prudek [Sat, 28 Mar 2015 11:32:10 +0000 (12:32 +0100)]
Predchozi reseni pouziti rychlejsich hodin pro vzorkovani pomalejsich hodin spi bylo chybne. 1) Hodiny nefungovaly 2) Tato chyba se neprojevila protoze hodiny spi (sclk) dal zustaly v sensitivite daneho procesu (i kdyz ne explicitne v zahlavi). Toto by melo byt funkcni reseni (asi ne nejjednodussi). Testovaci prenosy probehly v poradku. Zda se, ze nefunguje inicializase signalu? (signal test:std_logic_vector(4 downto 0):=01010) (SCLK 500KHz, GPCLK 2MHZ)

4 years agopridana komponenta qcounter
Martin Prudek [Fri, 27 Mar 2015 12:39:36 +0000 (13:39 +0100)]
pridana komponenta qcounter

4 years agoqcounter doplnen komentari
Martin Prudek [Fri, 27 Mar 2015 11:21:26 +0000 (12:21 +0100)]
qcounter doplnen komentari

4 years agopreformatovani
Martin Prudek [Fri, 27 Mar 2015 10:32:01 +0000 (11:32 +0100)]
preformatovani

4 years agozmena hodin pro spi z SCLK (500kHz) na GPCLK (2,4MHZ). Pomoci GPCLK je nyni 'vzorkova...
Martin Prudek [Fri, 27 Mar 2015 10:19:56 +0000 (11:19 +0100)]
zmena hodin pro spi z SCLK (500kHz) na GPCLK (2,4MHZ). Pomoci GPCLK je nyni 'vzorkovano', zda doslo ke zmene logicke hodnoty na SCLK. Takto je detekovana nabezna a sestupna hrana. Zakladni funkcnost overena na 'spi repeateru'. Pretrvavaji problemy s kodovanim (endianita & prazdny posuvny registr na zacatku prenosu..?).

4 years agoodstraneny testovaci vystupy na piny
Martin Prudek [Fri, 27 Mar 2015 09:56:11 +0000 (10:56 +0100)]
odstraneny testovaci vystupy na piny

4 years agopridan quadcount
Martin Prudek [Thu, 26 Mar 2015 16:58:17 +0000 (17:58 +0100)]
pridan quadcount

4 years agootestovan 'spi repeater' neuplny zpetny prenos (chybny prvni a posledni byte). Je...
Martin Prudek [Wed, 25 Mar 2015 19:13:55 +0000 (20:13 +0100)]
otestovan 'spi repeater' neuplny zpetny prenos (chybny prvni a posledni byte). Je treba ale pridat udalost na falling edge CS. Pouzivan CPHA=0 CPOL=0 (spi mod 0)

4 years agoHodinovy signal zesilen pomoci CLKINT. SPI otestovano smer rpi->fpga (pomoci vystupu...
Martin Prudek [Wed, 25 Mar 2015 18:51:04 +0000 (19:51 +0100)]
Hodinovy signal zesilen pomoci CLKINT. SPI otestovano smer rpi->fpga (pomoci vystupu na pinech)

4 years agoodstranen soubor STP
Martin Prudek [Sun, 22 Mar 2015 14:24:56 +0000 (15:24 +0100)]
odstranen soubor STP

4 years agotest spi - nefunkcni synteza pro sensitivity gpio11
Martin Prudek [Sun, 22 Mar 2015 14:05:37 +0000 (15:05 +0100)]
test spi - nefunkcni synteza pro sensitivity  gpio11

4 years agotestovani nahravani vhdl. Zmena logicke hodnoty na pinu 7 na HIGH
Martin Prudek [Sat, 21 Mar 2015 11:10:06 +0000 (12:10 +0100)]
testovani nahravani vhdl. Zmena logicke hodnoty na pinu 7 na HIGH

4 years agoprvni commit nove vetve - komentar miso
Martin Prudek [Fri, 20 Mar 2015 15:53:16 +0000 (16:53 +0100)]
prvni commit nove vetve - komentar miso

4 years agopridan stp soubor
Martin [Thu, 12 Mar 2015 14:22:44 +0000 (15:22 +0100)]
pridan stp soubor

4 years agoMerge remote-tracking branch 'origin/master'
prudemar [Fri, 6 Mar 2015 18:03:44 +0000 (19:03 +0100)]
Merge remote-tracking branch 'origin/master'

4 years agooprava cesty interpreteru
prudemar [Fri, 6 Mar 2015 18:00:39 +0000 (19:00 +0100)]
oprava cesty interpreteru

4 years agoMerge branch 'master' of rtime.felk.cvut.cz:/fpga/rpi-motor-control
Pavel Pisa [Tue, 3 Mar 2015 14:03:29 +0000 (15:03 +0100)]
Merge branch 'master' of rtime.felk.cvut.cz:/fpga/rpi-motor-control

4 years agoUpdate AGL program script to work with JT_USB6 in addition to JT_USB5 JTAG.
Pavel Pisa [Tue, 3 Mar 2015 14:02:16 +0000 (15:02 +0100)]
Update AGL program script to work with JT_USB6 in addition to JT_USB5 JTAG.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
4 years agopridan podadresar pmsm-control
prudemar [Fri, 13 Feb 2015 10:43:50 +0000 (11:43 +0100)]
pridan podadresar pmsm-control

4 years agoSTP file for AGL125 ERASE.
Pavel Pisa [Tue, 7 Oct 2014 13:39:35 +0000 (15:39 +0200)]
STP file for AGL125 ERASE.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
4 years agoSimple DC motor control with IRC decode by kernel module rpi_gpio_irc_module.
Pavel Pisa [Tue, 7 Oct 2014 13:38:45 +0000 (15:38 +0200)]
Simple DC motor control with IRC decode by kernel module rpi_gpio_irc_module.

The interface to RPi is same as for wire-wrapped
version described on LinTarget page

  http://lintarget.sourceforge.net/rpi-motor-control/index.html

Signed-off-by: Pavel Pisa <ppisa@pikron.com>