Pavel Pisa [Fri, 1 May 2015 15:48:28 +0000 (17:48 +0200)]
Change IRC recognition logic synchronous with main design clock.
Use of external, not synchronized signal event as
the trigger condition results in creation of additional
clock domain which can result in all kinds of hazard
conditions when used to manipulate with else synchronous
design state.
Pavel Pisa [Fri, 1 May 2015 14:59:49 +0000 (16:59 +0200)]
Include in PMSM design to implement safe behavior when external clocks are not present.
The PLL is configured to synthesize 200 MHz clock from 50 MHz input.
The clock monitor holds PWM outputs low if the external clocks are
not present. The reference lost is recognized 6 in 8 cycles
of 200 MHz synthesized clock as well.
Martin Prudek [Thu, 16 Apr 2015 14:02:32 +0000 (16:02 +0200)]
Attemp to solve bug. ADC channels association should be pwm1-ch0 pwm2-ch1 pwm3-ch2 (according to schema). In fact it is pwm1-ch1 pwm2-ch2 pwm3-ch0. Cant find the mistake.
Martin Prudek [Sat, 11 Apr 2015 09:14:13 +0000 (11:14 +0200)]
GPCLK frequency from RPi increased from 2Mhz to 50Mhz. To keep clk frequency for ADC lower then 3.2Mhz, freqency divider(divides by 8) have been added.
Martin Prudek [Sun, 5 Apr 2015 15:27:53 +0000 (17:27 +0200)]
Tested version of ADC state machine. Tested only to prove that 'something works'. Cannot verify measured data - so thah implemented communication protocol might not be workung.
Martin Prudek [Sat, 28 Mar 2015 11:32:10 +0000 (12:32 +0100)]
Predchozi reseni pouziti rychlejsich hodin pro vzorkovani pomalejsich hodin spi bylo chybne. 1) Hodiny nefungovaly 2) Tato chyba se neprojevila protoze hodiny spi (sclk) dal zustaly v sensitivite daneho procesu (i kdyz ne explicitne v zahlavi). Toto by melo byt funkcni reseni (asi ne nejjednodussi). Testovaci prenosy probehly v poradku. Zda se, ze nefunguje inicializase signalu? (signal test:std_logic_vector(4 downto 0):=01010) (SCLK 500KHz, GPCLK 2MHZ)
Martin Prudek [Fri, 27 Mar 2015 10:19:56 +0000 (11:19 +0100)]
zmena hodin pro spi z SCLK (500kHz) na GPCLK (2,4MHZ). Pomoci GPCLK je nyni 'vzorkovano', zda doslo ke zmene logicke hodnoty na SCLK. Takto je detekovana nabezna a sestupna hrana. Zakladni funkcnost overena na 'spi repeateru'. Pretrvavaji problemy s kodovanim (endianita & prazdny posuvny registr na zacatku prenosu..?).
Martin Prudek [Wed, 25 Mar 2015 19:13:55 +0000 (20:13 +0100)]
otestovan 'spi repeater' neuplny zpetny prenos (chybny prvni a posledni byte). Je treba ale pridat udalost na falling edge CS. Pouzivan CPHA=0 CPOL=0 (spi mod 0)