From: Martin Prudek <prudemar@fel.cvut.cz>
Date: Fri, 27 Mar 2015 12:39:36 +0000 (+0100)
Subject: pridana komponenta qcounter
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/commitdiff_plain/fd37bc240e6208a65ef1225e34093789c1231fd7

pridana komponenta qcounter
---

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index d6aa5fe..cb2b5e6 100644
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -102,12 +102,24 @@ architecture behavioral of rpi_mc_simple_dc is
 	component CLKINT
 		port (A: in std_logic; Y: out std_logic);
 	end component;
+	
+	component qcounter
+	port (
+		clock: in std_logic;
+		reset: in std_logic;
+		a0, b0: in std_logic;
+		qcount: out std_logic_vector (31 downto 0);
+		a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
+		ab_error: out std_logic
+	);
+	end component;
 
 	signal spiclk_old_lvl: std_logic :='0'; --pro detekci hrany SPI hodin
 	signal pwm_in, pwm_dir_in: std_logic;
 	signal spi_clk: std_logic;
 	signal gpio_clk: std_logic;
 	signal dat_reg : STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); --registr pro SPI
+	signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
 
 	--  attribute syn_noprune of gpio2 : signal is true;
 	--  attribute syn_preserve of gpio2 : signal is true;
@@ -131,6 +143,22 @@ begin
 		y => gpio_clk
 	);
 	
+	qcount: qcounter
+	port map (
+		clock => gpio_clk,
+		reset => '0',
+		a0 => irc_a,
+		b0 => irc_b,
+		qcount => position,
+		a_rise => open,
+		a_fall => open,
+		b_rise => open,
+		b_fall => open,
+		ab_event => open,
+		ab_error => open
+	);
+	
+	
 	--   pll: pll50to200
 	--     port map (
 	--       powerdown => '1',