From: Martin Prudek <prudemar@fel.cvut.cz>
Date: Sat, 28 Mar 2015 11:32:10 +0000 (+0100)
Subject: Predchozi reseni pouziti rychlejsich hodin pro vzorkovani pomalejsich hodin spi bylo... 
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/commitdiff_plain/ebcedee1e4891ae7e8863aab1d3f5b0a04a6dc64

Predchozi reseni pouziti rychlejsich hodin pro vzorkovani pomalejsich hodin spi bylo chybne. 1) Hodiny nefungovaly 2) Tato chyba se neprojevila protoze hodiny spi (sclk) dal zustaly v sensitivite daneho procesu (i kdyz ne explicitne v zahlavi). Toto by melo byt funkcni reseni (asi ne nejjednodussi). Testovaci prenosy probehly v poradku. Zda se, ze nefunguje inicializase signalu? (signal test:std_logic_vector(4 downto 0):=01010) (SCLK 500KHz, GPCLK 2MHZ)
---

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index cb2b5e6..7cdfac3 100644
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -14,7 +14,6 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.util.all;
-use work.qcounter.all;
 
 entity rpi_mc_simple_dc is
 port (
@@ -118,9 +117,14 @@ architecture behavioral of rpi_mc_simple_dc is
 	signal pwm_in, pwm_dir_in: std_logic;
 	signal spi_clk: std_logic;
 	signal gpio_clk: std_logic;
-	signal dat_reg : STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); --registr pro SPI
+	signal dat_reg : STD_LOGIC_VECTOR (7 downto 0):="10101010";
+	--"0000000100100011010001010110011110001001101010111100110111101111";
+		--(others=>'0'); --registr pro SPI
 	signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
-
+	signal spi_clk_rise: std_logic; --synchronni detekce nabezne hrany spi hodin
+	signal spi_clk_fall: std_logic; --synchronni detekce sestupne hrany spi hodin
+	signal ce0_int: std_logic;
+	
 	--  attribute syn_noprune of gpio2 : signal is true;
 	--  attribute syn_preserve of gpio2 : signal is true;
 	--  attribute syn_keep of gpio2 : signal is true;
@@ -143,6 +147,13 @@ begin
 		y => gpio_clk
 	);
 	
+	--zesileni signalu CE0
+	copyclk3: CLKINT
+	port map (
+		a => gpio7,
+		y => ce0_int
+	);
+	
 	qcount: qcounter
 	port map (
 		clock => gpio_clk,
@@ -190,8 +201,6 @@ begin
 	rs485_txd <= '1';
 	rs485_dir <= '0';
 
- 
-	--gpio24 <= dip_sw(1); --na desce je prohozene cislovani
 
 	shdn(1) <= '0';
 	shdn(2) <= '0';
@@ -201,23 +210,29 @@ begin
 	pwm(2) <= '0';
 	pwm(3) <= '0';
 
-
+	
+	process(gpio_clk)
+	begin
+		if gpio_clk= '1' and gpio_clk'event then
+			spiclk_old_lvl<=spi_clk;
+		end if;
+	end process;
+	spi_clk_rise <= (not spiclk_old_lvl) and spi_clk;
+	spi_clk_fall <= (not spi_clk) and spiclk_old_lvl; 
+ 
   
-	process (gpio_clk) 
+	process(spi_clk_fall,spi_clk_rise)
 	begin
-		--if (gpio11'event and gpio11 = '1') then  -- rising edge of SCK
-		if ((spi_clk = '1') and (spiclk_old_lvl = '0') ) then 
+		if (rising_edge(spi_clk_rise)) then --rising edge, faze cteni 
 			if (gpio7 = '0') then             -- SPI CS must be selected
 				-- shift serial data into dat_reg on each rising edge
 				-- of SCK, MSB first
 				dat_reg(7 downto 0) <= dat_reg(6 downto 0) & gpio10;
-				spiclk_old_lvl <= '1';
-	
-			end if;
-		elsif ((spi_clk = '0') and (spiclk_old_lvl = '1')) then
+				end if;
+		elsif (rising_edge(spi_clk_fall) ) then --falling edge, faze zapisu
 			if (gpio7 = '0') then
 				gpio9 <= dat_reg(7); --zapisujeme nejdriv MSB
-				spiclk_old_lvl <= '0';
+				
 			end if;
 		end if;
 	end process;